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US 4,727,506 AGranted
Digital scaling circuitry with truncation offset compensation
AssigneeRCA Corporation
InventorRussell T. Fling
Life of this patent
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Abstract
A scaling circuit for scaling PCM signals by factors less than one includes a bit-shift and truncating circuit. Roundoff error compensating circuitry adds an offset value to the samples to be scaled by the bit-shift circuitry to compensate for errors produced by truncation without rounding. The offset values are dithered to increase the apparent resolution of the system.
Claims10
Scaling circuitry for scaling pulse code modulated (PCM) signal samples comprising:
- a signal input port for applying said PCM signal samples;
- shift and truncating circuitry, having an input port and having an output port, said shift and truncating circuitry for shifting the bit significance of samples applied to its input to produce bit-shifted samples and truncating the bit-shifted samples to effect a scaling of samples applied to its input by 2.sup.-N where N is an integer, the bit-shifted and truncated samples corresponding to input samples scaled by a factor of 2.sup.-N ;
- an adder having a first input and an output terminal respectively coupled to said signal input port and the input port of said shift and truncating circuitry, and having a second input port;
- and
- means coupled to the second input port of said adder for applying compensating values to offset rounding errors generated by truncating said bit-shifted samples.
2 more elements
Dependencies are inferred from the claim text.