Hardware demand fetch cycle system interface

A memory management system for fetching a missing segment descriptor from a main memory, said system comprising:

• a system bus;
• said main memory coupled to said system bus and storing information in segments and storing a segment descriptor for each segment which includes a physical address of a first word of said each segment in said main memory;
• a memory management unit having means for detecting said missing segment descriptor and means for generating an address of a location in main memory of said missing segment descriptor in response to an indication from said detection means;
• and
• a CPU coupled to said system bus and said memory management unit and including:
• (a) means for stalling a system clock upon receiving said indication of said missing segment descriptor for suspending normal operation of said CPU;
• (b) means for connecting to said system bus for sending said address received from said memory management unit to said main memory, said address indicating a location of said missing segment descriptor;
• (c) means for receiving said missing segment descriptor read from said location in main memory via said system bus for storage in a translation table in said memory management unit;
• and
• (d) means for restarting said system clock for performing a required operation on a word in said main memory in a segment specified by said missing segment descriptor.

A data processing system includes a central processing unit (CPU), a main memory coupled in common to a system bus, and a memory management unit (EMMU) coupled to said CPU, said main memory storing information words in segments, each word location of said segments being addressed by a physical address of a first word location of said segments to which is added a displacement, said EMMU including a translation table for storing segment descriptors which include said physical address, said EMMU being responsive to a logical address from said CPU for reading out one of said segment descriptors from said translation table, said EMMU and said CPU having apparatus for fetching said one of said segment descriptors from main memory via said system bus if said one of said segment descriptors is not found in said translation table, said apparatus comprising:

• missing segment descriptor means for generating a first signal indicating that a requested segment descriptor is not present in said translation table;
• clock means coupled to said missing segment descriptor and responsive to said first signal which stalls a cylic clock signal thereby suspending normal operation of said EMMU and said CPU;
• address generating means coupled to said missing segment descriptor means and responsive to said first signal for generating an address of a location in said main memory storing said requested segment descriptor;
• bus connect means coupled to said system bus and said address generating means and responsive to said first signal for sending said address over system bus to said main memory and receiving said requested segment decriptor via said system bus for storage in said translation table, said bus connect means further receiving a second signal;
• and
• restart means coupled to said system bus and responsive to said second signal for restarting said cyclic clock signal for continuing the operation requiring said requested segment descriptor.