Memory addressing device

A device for sequentially addressing a memory with a stream of address words, the address words being successively delivered to the memory at a predetermined clock-period rate and each address word including first and second address words composed of least significant bits and most significant bits of the address word, respectively, the first and second address words being multiplexed, comprising

• (a) means for deriving a predetermined digital signal carrying words that are synchronous with the first address words;
• (b) means connected with said deriving means for receiving the first and second address words and said predetermined signal words for alternately incrementing the first and second address words into first and second incremented address words, respectively, the first address words being incremented in response to said predetermined signal words, respectively, and each of the second address words being incremented by 1 when the first address word included in the address word comprising the second address word has bits all equal to "1";
• and
• (c) shift means looping said incrementing means for receiving first and second incremented address words and delivering them after a predetermined number of clock periods as new first and second address words to be incremented by said incrementing means, said first and second incremented address words successively produced by said incrementing means composing said stream of address words.