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US 4,727,468 AGranted
Digital PWM control circuit
AssigneeKabushiki Kaisha Toshiba
InventorKatsumi Maekawa
Life of this patent
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Abstract
The PWM-controlled circuit includes an up/down counter and utilizes the fact that, when a numerical value is a complementary binary value, the sign is indicated by its most significant bit (sign bit). In the PWM control circuit, the up/down counter is controlled so that when its preset input receives a reference signal, a PWM signal of a duty factor proportional to the reference signal is directly obtained from the most significant bit of the output count.
Claims10
A digital PWM control circuit comprising:
- reference signal generating means for generating a binary reference signal having N bits and including a sign bit, said N being an integer not less than 1;
- control signal generating means for generating a load signal at every predetermined period and an enable signal at a predetermined timing;
- and
- N+a bit counter means, coupled to said reference signal generating means and said control signal generating means, for receiving N+a bit preset data to be preset therein upon generation of the load signal, the N+a bit preset data being obtained by combining the N bit binary reference signal and a-bit data having the same content as the sign bit of the binary reference signal, said a being an integer not less than 1, and said N+a bit counter means counting a predetermined clock signal under generation of the enable signal, wherein any bit data of Nth to (N+a)th bit of said counter means is provided as a PWM control signal.
1 more element
A digital PWM control circuit comprising:
- reference signal generating means for generating a binary reference signal having N bits and including a sign bit, said N being an integer not less than 1;
- control signal generating means for generating a load signal at every predetermined period and a clock signal;
- and
- N+a bit counter means, coupled to said reference signal generating means and said control signal generating means, for receiving N+a bit preset data to be preset therein upon generation of the load signal, the N+a bit preset data being obtained by combining the N bit binary reference signal whose most significant bit is level-inverted and a-bit data having a given content, said a being an integer not less than 1, and said N+a bit counter means counting the clock signal, wherein any bit data of Nth to (N+a)th bit of said counter means is provided as a PWM control signal.
1 more element
Dependencies are inferred from the claim text.