A VDP timing signal generator producing clock signals in phase with produced video sync signals and displaying the inphase condition

Abstract

A timing signal generator for use in a system reproducing video format signals such as a video disc player, the timing signals being used to control a still-with-sound (SWS) processor operating with the video disc player. The timing signal generator includes a synchronizing signal separator circuit for extracting the vertical and composite synchronizing signals from the reproduced video signal. The extracted vertical synchronizing signal is input to a phase-locked loop which produces a system clock synchronized to the vertical synchronizing signal. A horizontal synchronizing circuit receives the system clock signal and the composite synchronizing signal to produce a timing signal in phase with the system clock within the horizontal period. A vertical synchronizing circuit receives the extracted vertical synchronizing signal and the output of the horizontal synchronizing circuit to produce a timing signal synchronous with the system clock within the vertical period. A timing signal generating circuit produces timing signals for the SWS processor from the timing signals produced by the horizontal and vertical synchronizing circuits. In addition, a synchronous lock detecting circuit connected to a suitable display, produces signals indicating synchronism of the extracted vertical synchronizing signals with the timing signal produced by the vertical synchronizing circuit of the timing signal generator.

Dependencies are inferred from the claim text.