Video data processing circuit employing plural parallel-to-serial converters and look-up tables

A video data processing circuit for use with an image display unit for displaying an image on a display area of the image display unit in accordance with plural video data which are respectively representative of pixels constituting the display area, comprising:

• a first number of memory means, each addressable by the same addresses, for storing the video data and for being simultaneously accessed to output at a time multiple pieces of data equal to said first number from among the stored video data;
• a second number of parallel-to-serial converting means provided correspondingly to said first number of memory means, the second number being an integral fraction of the first number, each of said second number of parallel-to-serial converting means being coupled for storing corresponding ones from among said multiple pieces of data and then for serially outputting said corresponding ones at a first predetermined rate;
• a plurality of look-up table means provided in a number equal to said second number, each look-up table means being responsive to said corresponding ones outputted from a corresponding one of the parallel-to-serial converting means and successively converting the received ones into image data;
• and
• selector means for being supplied with said image data respectively from said plurality of look-up table means and outputting the supplied image data one by one at a second predetermined rate which is greater than said first predetermined rate, the image being displayed on the image display unit in accordance with said image data outputted from said selector means.

A video data processing circuit, comprising:

• a plurality of video memory means, each for storing video data formed of plural groups, wherein each group is comprised of a predetermined number of bits of data;
• a plurality of sets of parallel-to-serial converters, one set provided separately for each of said memory means, each set of converters receiving a group of bits in parallel from an associated memory means, wherein each set includes at least a first converter which receives a first subset of the respective group and a second converter which receives a second subset of the respective group, each converter providing a serial output at a first rate, wherein the output of each converter in a set is combined in parallel with the output of a corresponding converter in every other set to form a plurality of multi-bit signals in which the number of bits is equal to the number of sets;
• a plurality of look-up table means, equal in number to the number of converters in a set and each receiving a different one of said multi-bit signals, for successively converting the received multi-bit signals into image data;
• and
• selector means supplied in parallel with the image data from each lookup table means and outputting said data one by one at a second rate equal to the first rate divided by the number of converters per set.