Fault simulation for differential cascode voltage switches
AssigneeInternational Business Machines Corporation
InventorsZeev Barazilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman
Life of this patent
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Abstract
A method of simulating a differential cascode voltage switch circuit (domino circuit) by replacing each switch-level logic tree by a three-section Boolean tree. In each section, a switch is replaced by an AND gate. The first and third section pass signals in one direction and the second section passes signals in the opposite directions. The three sections are interconnected end to end. Various faults can be simulated by holding selected internal signals at faulty values.
Claims9
A method for transforming a switch level representation of a circuit to a Boolean representation of said circuit, said switch level representation comprising one or more logic trees, each said tree comprising one or more differential pairs, each said differential pair comprising a first switch and a second switch, each said first switch having a first switch input and a first switch output, each said second switch having a second switch input and a second switch output, said first and second switch inputs of a differential pair being connected to a common switch point, each said common switch point being connected to one of two switch outputs of at least one other differential pair or to a switch potential reference point, each said switch output being connected to either a common switch point of another differential pair or to a switch tree output, each first and each second switch of each differential pair being controlled by a first and a second major switch net respectively, intended to be of complementary values, said major switch nets being connected to either a primary input or a switch tree output of another switch tree, said method comprising the steps of:
- representing each switch by a Boolean gate in a first series interconnected similarly to said logic tree;
- representing each switch by a Boolean gate in a second series interconnected similarly to said logic tree;
- representing each switch by a Boolean gate in a third series interconnected similarly to said logic tree;
- interconnecting said first and second series at two points corresponding to said two switch tree outputs;
- and
- interconnecting said second and third series at points corresponding to said switch reference point and to said common switch points.
A smethod for transforming a switch level representation of a circuit to a Boolean representation of said circuit, said switch level representation comprising one or more logic trees, each said tree comprising one or more differential pairs, each said differential pair comprising a first switch and a second switch, each said first switch having a first switch input and a first switch output, each said second switch having a second switch input and a second switch output, said first and second switch inputs of a differential pair being connected to a common switch point, each said common switch point being connected to a switch output of at least one other differential pair or to a switch potential reference point, each said switch output being connected to either a common switch point of another differential pair or to one of two switch tree outputs, each switch tree output being an input to an inverting output circuit, each first and each second switch of each differential pair being controlled by a first and a second major switch net respectively, intended to be of complementary values, said major switch nets being connected either to a primary input or a circuit output of another switch tree, said method comprising the steps of:
- representing each said differential pair by a first Boolean block of a first AND gate and a second AND gate, first inputs of said first and second AND gates being connected together to a Boolean common point, and second inputs of said first and second AND gates being connected to first and second major Boolean nets respectively;
- interconnecting all Boolean blocks representing said differential pairs
- similarly to the interconnections of said differential pairs in said logic tree, wherein:
- a connection to a said switch common point is replaced by a connection to a said Boolean common point;
- a connection to a said first or a said second major switch net is replaced by a connection to a said first or a said second major Boolean net respectively;
- a connection to a said first or said second switch output is replaced by a connection to an output of a said first or a second AND gate respectively;
- and
- a connection between outputs of a plurality of switches and a switch common point or a switch tree output is replaced by connections from outputs of a plurality of first or second AND gates representing said plurality of switches to inputs of a first dotting OR gate and by a connection from an from an output of said first dotting OR gate to a Boolean common point representing said switch common point or switch tree output.
Dependencies are inferred from the claim text.