US 4,727,268 AGranted

Logic circuitry having two programmable interconnection arrays

AssigneeKabushiki Kaisha Toshiba

InventorChikahiro Hori

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Abstract

According to this invention a plurality of kinds of circuit blocks is formed as a circuit block area on a chip substrate to have a desired logic function. An array of signal output wires and array of signal input wires are formed adjacent the circuit block area such that these arrays intersect each other. First switching elements are each formed at a corresponding intersection of the signal output wire and signal input wire. An LSI device having a desired logic function can be implemented by electrically and fixedly writing an ON or OFF state of the first switching element. A first control wire and second control wire are provided adjacent to the circuit block area with the wire arranged parallel to the signal output wire and the wire arranged parallel to the signal input wire. Second switching elements are arranged at intersections of the first control wire and the signal input wires and at intersections of the second control wire and signal output wires. To a given circuit block, the output signals of the other circuit blocks can be supplied in a time-division fashion by controlling the second switching element, in real time, by virtue of a control circuit.

Claims2

Dependent claims

A semiconductor integrated circuit device comprising:

(a) a semiconductor substrate;
(b) a plurality of kinds of circuit blocks each formed on said substrate and having its own logic function;
(c) a plurality of signal input wires formed on said substrate in a direction parallel to each other and connected to respective ones of signal input terminals of said circuit blocks.
(d) a plurality of signal output wires formed on said substrate, each arranged in a direction intersecting the signal input wire and electrically insulated from the signal input wire;
(e) a plurality of branch lines each formed on said substrate branched from the signal output line, and connected to a signal output terminal of respective ones of said circuit blocks;
(f) a first switching element array comprised of switching elements on said substrate, each of which is arranged at a respective intersection between the signal input wire and signal output wire and in which a connection state between the signal input wire and the signal output wire is determined by electrically writing an ON or OFF state;
(g) a first control wire formed on the substrate in a direction parallel to the signal output line;
(h) a second control wire formed on the substrate in a direction parallel to the signal inputs wire;
(i) a second switching element array formed on said substrate and comprised of switching elements at respective intersections of said first control wire and said signal input wires and at respective intersections of said second control wire and said signal output wires, a state of connection between said first control wire and the signal input wire and that between said second control wire and the signal output wires being determined by an ON/OFF control;
and
(j) a switching element control circuit formed on said substrate and coupled for controlling the second switching element in real time.

8 more elements

Dependencies are inferred from the claim text.