US 4,727,048 A · Process for making isolated semiconductor structure

Abstract

An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Claims17

Dependent claims

A method for forming an integrated circuit comprising the following steps:

forming at least a first and a second active device in a semiconductor substrate;
forming a groove in said substrate between said first and said second active devices;
reacting silane and germane with a source of oxygen atoms so that a glass layer comprising GeO.sub.2 and SiO.sub.2 is deposited over the structure resulting from the preceding steps, said glass layer being between 47.5 mole percent and 50 mole percent GeO.sub.2 ;
and
reflowing said glass layer at a temperature sufficiently low to substantially prevent diffusion of dopants in said active devices.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

06/891,792Filed 2 Oct 1986 · continuation

Priority

16 Mar 1981

Granted

23 Feb 1988

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10P 14/6334
Deposition from the gas or vapour phase: using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
H10P 14/6682
The precursor containing a compound comprising Si: the compound being a silane, e.g. disilane, methylsilane or chlorosilane
H10P 95/00
Generic processes or apparatus for manufacture or treatments not covered by the
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations

Family

Serial243,987Parent of this continuation-in-part · filed 16 Mar 1981

Serial362,347Parent of this continuation · filed 26 Mar 1982

Serial773,842Parent of this continuation · filed 6 Sep 1985

US 4,630,343 AParent of this continuation

US 4,727,048 AThis patent

From the US filing history. Foreign family members aren’t listed.

Process for making isolated semiconductor structure

Life of this patent

Process for making isolated semiconductor structure

Life of this patent

Abstract

Claims17