US 4,727,045 A · Plugged poly silicon resistor load for static random access memory cells

Abstract

An improved process for fabricating a static RAM cell having a polysilicon load resistance is provided. Following formation of source, gate and drain regions, a planarized dielectric structure is formed over the junction regions, and via openings which expose portions of the source and drain regions are created. The via openings are filled with polysilicon interconnects, appropriately doped for low resistance contacts. Where the contact includes a resistor load, the polysilicon is not doped. Thus, the prior art approach of providing doped and undoped regions along the same polysilicon interconnect is not employed. Rather, the doped and undoped regions are physically separated. Consequently, the minimum length of the poly load is limited only by the ability to form via openings of small dimensions.

Claims14

Dependent claims

A process for fabricating at least one static RAM cell on a substrate, comprising junction regions disposed in a major surface of said substrate and a load resistor electrically contacting one of said junction regions, said process including:

(a) forming a planar dielectric layer on said major surface;
(b) forming via openings in said dielectric layer to expose portions of said junction regions;
(c) depositing undoped polysilicon in one of said via openings to form said load resistor in contact with said junction region and forming low resistance material interconnects in each of the remaining via openings to electrically contact the remaining junction regions;
and
(d) forming separate metal contacts to each of said polysilicon and said low resistance material interconnects.

2 more elements

A process for fabricating at least one static RAM cell, each comprising a pair of complementary metal-oxide semiconductor transistors formed in a major surface of substrate, each transistor defined by source, gate and drain regions, and a load resistor in series with a drain region, said process including:

(a) forming a planarized dielectric layer consisting essentially of a material selected from the group consisting of silicon dioxide and silicon nitride on said surface;
(b) forming via openings in said planarized layer to expose portions of said source and drain regions;
(c) depositing polysilicon interconnects in said via openings;
(d) doping said polysilicon to match the polarity of the junction region underlying each said aperture, other than said polysilicon comprising said load resistor;
and
(e) forming separate metal contacts to each said polysilicon interconnect.

3 more elements

Dependencies are inferred from the claim text.

Plugged poly silicon resistor load for static random access memory cells

Life of this patent

Plugged poly silicon resistor load for static random access memory cells

Life of this patent

Abstract

Claims14