Digital filter switch for data receiver

#The present invention relates to a digital filter switch for a data receiver, and more particularly to a switch for a data receiver having two paths following an analog-to-digital converter each containing a band-pass filter.

#The periodical "NTZ", Vol. 36 (1983), No. 12, pp. 806-808 describes a method for digital FM-demodulation under the title "Ein digitaler Demodulator fur aequidistant abgetastete FM-Signale". In addition, the periodical "IEEE Trans. Communications COM-29" (1981), No. 7, p. 1061 and the periodical "NTZ", Vol. 37 (1984), No. 7, p. 414 both describe digital detectors which may be used for detecting zero axis crossings in connection with a data receiver. However, these circuits, when constructed in practical form, lead to relatively great circuit complexity. It is thereby desirable to construct a digital filter switch which is more simply and economically realized.

#A principal object of the present invention is to provide a data receiver using a digital filter switch in which excess circuit complexity is avoided as much as possible.

#Reference will now be made to the accompanying drawing in which:

#FIG. 1 is a schematic diagram of a demodulator incorporating a digital filter switch incorporating an illustrative embodiment of the present invention having an analog-to-digital converter and a discriminator;

#FIG. 2 is a functional block diagram of a transversal third degree filter having three delay elements;

#Referring now to FIG. 1, a signal supplied to an input terminal 1 is supplied to an anti-aliasing low-pass filter 8 which is followed by an analog-to-digital converter 9. The function of the low-pass filter 8 is to prevent periodic attenuation variations.

#The analog-to-digital converter 9 produces output signals in digital form as e.sub.1 (t) and e.sub.2 (t). A first path A, for example, a 1200 Hz path, incorporates a band-pass filter 3, whereas a second B path for 1800 Hz incorporates a band-pass filter 4. The responses of the band-pass filters 3 and 4 are respectively h.sub.BP1 (t) and h.sub.BP2 (t), as indicated in FIG. 1. Signals b.sub.1 (t) and b.sub.2 (t) appear at the outputs of the band-pass filters 3 and 4. These signal are supplied to squaring devices 5 which follow each of the band-pass filters 3 and 4 which supply respectively signals c.sub.1 (t) and c.sub.2 (t) as outputs, which represent the product of the signals b.sub.1 (t) and b.sub.1 (t), and the product of the signals b.sub.2 (t) and b.sub.2 (t), respectively. These two outputs are supplied to inputs of an adder unit 6, which performs a subtraction by inverting the sign of one of the operands before adding. The adder produces a difference output signal s(t) which is connected to the input of a low-pass filter 7 (TP) which has a response indicated in FIG. 1 as h.sub.TP (t). It produces an output signal a(t) which is applied to the input of a discriminator 2 which serves to synchronize the discriminator clock via the zero axis crossings of the signal a(t) and produces the output messages. The detailed structure of the discriminator is not described because it is not necessary for an understanding of the present invention.

#The band-pass filter 3 is tuned to the separating frequency f.sub.1 of 1200 Hz, whereas the band-pass filter 4 is tuned to the character frequency f.sub.2 of 1800 Hz. The function of the low-pass filter 7 (TP) is to attenuate harmonics which may be present in the difference signal produced at the output of the adder unit 6.