US 4,722,084 A · Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits

Abstract

An array reconfiguration apparatus is employed in large integrated circuits and large systems. The apparatus makes use of spare wires and/or computation elements which are incorporated in the array. The apparatus uses spare wires in place of defective wires and/or the apparatus uses spare computation elements in place of defective computation elements so that an operational system may be created in spite of the occurrence of numerous manufacturing or lifetime faults. The excess wires are utilized as data input and output lines and as such each data line is associated with a bidirectional buffer/receiver (B/R). The bidirectional B/R's are capable of transmitting data in either direction as from an input terminal to an output terminal or vice versa. Each data line is connected to a bidirectional multiplexing device which has a control input. Control logic means has dynamically stored therein the assignment of each significant wire and each computation element. Only unreliable wires as between integrated circuits are switchable. The control logic selects operational elements as well as operational data lines and hence uses the spare data lines to make connections between the redundant elements on the circuit board so that an array configuration can be implemented in spite of multiple defects on the overall circuit board. The invention further discloses a simple method for computing the assignments of cells and wires to avoid the defects.

Claims22

Dependent claims

Array configuration apparatus for use in reconfiguring large integrated circuit systems of the type including arrays of distinct logic circuits arranged in rows, with each row consisting of N identical circuits for connecting to N identical circuits in another row by means of bidirectional data lines, wherein in order to provide an operative array, there is required that connection be made between N-X operational circuits in one row and N-X operational circuits in the next row, with said connections being made by N-X data lines, where X is the number of defects plus unused spares and is a positive integer less than N and where N-X is the number of data bits to be coupled between said rows, comprising:

first means operative to select N-X operational circuits in each of said rows,
second means operative to select N-X operational data lines for connecting said rows to each other, and
control means responsive to the selection of said first and second means to bidirectionally connect said N-X operational circuits in each row selected by said first means to one another via said N-X data lines selected by said second means to enable the bidirectional transfer of said N-X bits from row to row.

Array reconfiguration apparatus for use in reconfiguring large integrated circuit systems of the type including arrays of distinct logic circuits, each of said arrays of distinct logic circuits being characterized in having a plurality of identical circuit structures necessary to perform given arithmetic operations with said plurality of circuit structures in each array having input and output data lines for coupling to other circuit structures in said array with said array further characterized in that a given number N of identical circuit structures is neccessary to form an operative array and that a given number of data lines are necessary to couple said structures within said arrays, said arrays being formed so that each structure contains an excess M of identical circuit structures, with an excess X of data lines, where M and X are positive integers and are selected in accordance with the reliability associated with fabricating said array by integrated circuit techniques, comprising:

a plurality of bidirectional buffer/receivers each separate one coupled to a separate input and output data line to allow said associated line to receive or transmit data, said bidirectional buffer/receivers each having an input terminal and an output terminal, with the input terminal coupled to said data line,
a plurality of bidirectional buffer/receivers each separate one coupled to a separate input and output data line to allow said associated line to receive or transmit data, said bidirectional buffer/receivers each having an input terminal and an output terminal, with the input terminal coupled to said data line,
a given number of bidirectional multiplexing means each having an input and output terminal each capable of the bidirectional transmission of data between said terminals, each of said bidirectional multiplexing means having a control terminal for selecting any one in said given number, with said input terminals of said bidirectional multiplexing means coupled together and connected to the output terminal of an associated buffer receiver and with the output terminals of said bidirectional multiplexing means each separately coupled to one associated excess data line, and
control logic means coupled to said control terminals of said bidirectional multiplexing means and operative to select any one of said given number of bidirectional multiplexing means to thereby direct said associated data line to any one of said associated excess data lines, whereby said excess data lines can transmit data to said other identical circuit configurations when selected.

1 more element

Dependencies are inferred from the claim text.

Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits

Life of this patent

Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits

Life of this patent

Abstract

Claims22