Semiconductor memory having a dynamic level detecting means for detecting a level of a word line

A semiconductor memory comprising:

• a memory array which has a plurality of memory cells and a plurality of selection lines coupled to said memory cells;
• a driver circuit whose output terminal is coupled to one end of each selection line for selecting predetermined memory cells by providing an output signal to a predetermined selection line;
• a voltage detector circuit constructed of a first MOSFET whose gate receives an output signal of said driver circuit through said predetermined selection line, an output node coupled in series with the source-drain path of the first MOSFET, a second MOSFET which is on/off-controlled by a timing signal, wherein said first and second MOSFETs are connected in series between the output node and one terminal of a power source, and a third MOSFET which is on/off-controlled complementarily to said second MOSFET and which is connected between another terminal of the power source and the output node;
• and
• a fourth MOSFET which is interposed between said another terminal of the power source and the gate of said first MOSFET, and which is brought into an "on" state by an output of the output node at a predetermined time when said second MOSFET has been brought into an "on" state and when a gate potential of said first MOSFET has exceeded a predetermined level