US 4,718,035 AGranted

Logic operation circuit having an exclusive-OR circuit

AssigneeKabushiki Kaisha Toshiba

InventorsHiroyuki Hara, Yasuhiro Sugimoto

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Abstract

A logic operation circuit includes an exclusive-OR circuit for receiving first and second input signals, a carry output signal selection circuit for selectively generating a sum signal or an inverted signal thereof as a carry output signal in accordance with an output signal from the exclusive-OR circuit, and a carry output signal selection circuit for selectively generating a carry input signal or the first input signal as a sum signal in accordance with the output signal from the exclusive-OR circuit. The sum signal selection circuit has first and second differential amplifiers respectively driven by first and second output signals which are inverted to each other and received from the exclusive-OR circuit so as to generate the sum signal in accordance with the carry input signal, and the carry input signal selection circuit has third and fourth differential amplifiers respectively driven in accordance with the first and second output signals from the exclusive-OR circuit so as to generate carry output signals in accordance with the first input signal and carry input signal, respectively.

Claims4

Dependent claims

A logic operation circuit comprising:

an exclusive-OR circuit for generating first and second output signals which are inverted to each other in accordance with first and second input signal;
a sum signal selection circuit having first and second differential amplifier circuits which each include a plurality of transistors having emitter-collector paths connected between a power source terminal and the output terminals of said exclusive OR circuit and are driven by the first and second output signals from said exclusive-OR circuit to generate a sum signal in accordance with a carry input signal;
and
a carry output signal selection circuit including a third differential amplifier circuit driven by the first output signal from said exclusive-OR circuit to generate a carry output signal in accordance with the first input signal, and a fourth differential amplifier circuit driven in accordance with the second output signal from said exclusive-OR circuit to generate the carry output signal in accordance with the carry input signal, each of said third and fourth differential amplifier circuits including a plurality of transistors having emitter-collector paths connected between the power source terminal and the output terminals of said exclusive-OR circuit.

1 more element

Dependencies are inferred from the claim text.