Adaptively synchronized ring network for data communication

In a ring communication system comprising a unidirectional closed ring signal path including a plurality of network interface units (NIU's) coupled in series at spaced apart locations along the signal path for receiving and transmitting data throughout the closed signal path, wherein each of the NIU's includes:

• input demodulator means including means for receiving a receive modulated signal directed towards the NIU on the receive signal path and means for generating a receive clock signal and a receive data signal from the receive modulated signal;
• output modulator means including means for generating a transmit modulated signal from a transmit data signal and a transmit clock signal, and means for transmitting the transmit modulated signal directed away from the NIU on the signal path;
• an elastic storage buffer (ESB) having a buffer input line adapted to receive the receive data signal from the input demodulator means and having a buffer output line adapted to apply the transmit data signal to the output modulator means, and wherein the ESB is a first-in/first-out (FIFO) storage element including means for storing the receiving data signal at an input data bit rate determined by the receive clock and means for transferring the stored data to the output modulator means on a first-in/first-out basis at an output data bit rate determined by the transmit clock;
• and
• controller means for generating the transmit clock as a function of the average number of data bit time periods in the storage element, wherein the elastic storage buffer includes:
• (a) a first register including a first input line, a first output line, input means for transferring data on said first input line into said first register, and first output means for transferring data from said first register to said first output line;
• (b) a second register including a second input line, a second output line, input means for transferring data on said second input line into said second register, and second output means for transferring data from said second register to said second output line;
• (c) first switch means for alternately coupling the receive data signal on the buffer input line to said first and second input lines during alternate clock periods of the receive data clock signal;
• (d) second switch means for alternately coupling said first and second output lines to the output modulator means by way of the buffer output line during alternate clock periods of the transmit clock signal;
• and further comprising the controller means including,
• (e) comparator means for generating a reference signal representative of the instantaneous average number of bits in said first and second registers by monitoring the switching states of said first and second switch means;
• (f) filter means responsive to said reference signal for generating a filtered signal therefrom;
• and,
• (g) a voltage controlled oscillator responsive to said filtered signal and including means for generating a VCO signal at a frequency related to the amplitude of said filtered signal, said VCO signal corresponding to the transmit clock signal.

In a computer communications network comprising a unidirectional closed ring signal path having a plurality of network interface units (NIU's) coupled in series at spaced apart locations along the signal path for interfacing a computer to the network by receiving and transmitting data throughout the closed signal path wherein each of the NIU's includes:

• an input demodulator including means for receiving a receive modulated signal directed towards the NIU on the receive signal path and means for generating a receive clock signal and a receive data signal from the receive modulated signal;
• an output modulator including means for generating a transmit modulated signal from a transmit data signal and a transmit clock signal, and means for transmitting the transmit modulated signal directed away from the NIU on the signal path;
• a first-in/first-out (FIFO) storage element having an input line adapted to receive the receive data signal from the input demodulator means and having an output line adapted to apply the transmit data signal to the output modulator means, and wherein the FIFO is adapted for storing the receive data signal at an input data bit rate determined by the receive clock and for transferring the stored data to the output modulator means at an output data bit rate determined by the transmit clock;
• and
• a controller for generating the transmit clock as a function of the average number of data bits in the FIFO, wherein
• (a) the FIFO includes:
• (a1) a first bistable flip-flop for holding a single bit and having a first input line, a first output line, input means for transferring data on said first input line into said first flip-flop, and first output means for transferring data from said first flip-flop to said first output line;
• (a2) a second bistable flip-flop for holding a single bit and having a second input line, a second output line, input means for transferring data on said second input line into said second flip-flop, and second output means for transferring data from said second flip-flop to said second output line;
• (a3) first switch means for alternately coupling the receive data signal on the FIFO input line to said first and second input line during alternate clock periods of the receive data clock signal;
• and
• (a4) second switch means for alternately coupling said first and second output lines to the output modulator means by way of the FIFO output line during alternate clock periods of the transmit clock signal;
• and additionally comprising,
• (b) and wherein the controller includes:
• (b1) counter means connected to said first and second switch means for monitoring and counting the switching states of said first and second switch means;
• (b2) comparator means connected to said counter means for generating a reference signal representative of the instantaneous average number of bits in said first and second flip-flops;
• (b3) filter means responsive to said reference signal for generating a filtered signal therefrom;
• and,
• (b4) voltage controlled oscillator means responsive to said filtered signal for generating the transmit clock as a VCO signal at a frequency related to said filtered signal thus varying the average number of data bits in said two flip-flops such that the output bit rate from said flip-flops approaches the input bit rate to said flip-flops whereby the cumulative controlling action of the interfacing units on the network causes the data transmission throughout the signal path to be stabilized at a substantially common bit rate causing the sum of all delays of the data bits in the signal path ring, including those due to passage of the bits through said flip-flops, to become a multiple of 360 degrees.

In a ring communication system comprising a unidirectional closed ring signal path including a plurality of network interface units (NIU's) coupled in series at spaced apart locations along the signal path for receiving and transmitting data throughout the closed signal path, wherein each of the NIU's includes input demodulator means including means for receiving a receive modulated signal directed towards the NIU on the receive signal path and means for generating a receive clock signal and a receive data signal from the receive modulated signal;

• output modulator means including means for generating a transmit modulated signal from a transmit data signal and a transmit clock signal, and means for transmitting the transmit modulated signal directed away from the NIU on the signal path;
• an elastic storage buffer (ESB) having a buffer input line adapted to receive the receive data signal from the input demodulator means and having a buffer output line adapted to apply the transmit data signal to the output modulator means, and wherein the ESB is a first-in/first-out (FIFO) storage element including means for storing the receive data signal at an input data bit rate determined by the receive clock and including at least a first and second register each having an input and an output line and means for transferring the stored data to the output modulator means on a first-in/first-out basis at an output data bit rate determined by the transmit clock;
• and, controller means for generating the transmit clock the method of transferring data through a network interface unit as part of a synchronous ring communication system comprising the steps of:
• (a) transferring data on the first input line into the first register, and transferring data from the first register to the first output line;
• (b) transferring data on the second input line into the second register, and transferring data from the second register to the second output line;
• (c) alternately coupling the receive data signal on the buffer input line to the first and second input lines during alternate clock periods of the receive data clocks ignal;
• (d) alternately coupling the first and second output lines to the output modulator means by way of the buffer output line during alternate clock periods of the transmit clock signal;
• and further comprising the controller means including,
• (e) generating a reference signal representative of the instantaneous average number of bits in the first and second registers by monitoring the switching states of the first and second switch means;
• (f) generating a filtered signal from the reference signal;
• and,
• (g) generating a VCO signal at a frequency related to the amplitude of the filtered signal and using the VCO signal for the transmit clock signal.

A method of synchronous data communication in a ring communication system of serial connected network interface units comprising the steps of:

• repeating data at each said network interface unit, including the steps of:
• receiving data at a receive clock signal rate;
• storing the received data in a storage buffer;
• generating a transmit clock signal;
• monotonically adjusting the frequency of said transmit clock signal in response to the phase difference of said receive clock signal relative to said transmit clock signal;
• and
• transmitting the stored data according to said transmit clock signal, wherein
• said step of adjusting provides a delay between the data transmitted by a specific network interface unit and the same data received by the same network interface unit propagated through the ring communication system selected to substantially correspond to integer multiples of the receive clock signal interval of a network interface unit;
• and
• said step of adjusting, in at least one network interface unit, includes adjusting the phase of the transmit clock signal to have a residual delay in said network interface unit providing a stable ring communication system having at least a nondiverging range of transmit clock rates at all network interface units.

A ring communication system comprising:

• a plurality of network interface units connected in series along a closed signal path ring for receiving, storing, and retransmitting data bits along the closed signal path,
• each including a feedback control means for continuously and simultaneously adjusting both the data retransmission rate and the phase delay between the received data and the retransmitted data wherein:
• the data retransmission rate continuously approaches the received data rate,
• the phase delay between received data bits and their retransmitted counterparts is a monotonic function of the retransmitted data rate and in the range at least from 0 to 360 degrees based on the retransmitted data rate, and
• the closed loop transfer function of the feedback control means has steady state closed loop transfer function that is for all inut values less than unity so that by cumulative action of the varying of the retransmitted data bit rate and the varying phse delay between the received data and the retransmitted data of each of the plurality of network interface units, data transmission throughout the signal path ring is stabilized at a substantially common bit rate.