Multiple port integrated DMA and interrupt controller and arbitrator
AssigneeInternational Business Machines Corporation
InventorsGilbert S. Burrus, Jr., Ronald J. Cooper, Michael R. Marr, John C. Pescatore, Mario A. Marsico
Life of this patent
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Abstract
Both DMA access and character interrupt driven access modes of service are provided to multiple communication ports by an integrated arbitration DMA/interrupt controller utilizing its own resident randomly accessible memory. Pipelined logic control architecture for handling service mode adaptations for each individual port and for managing memory accesses to main system memory enables the use of the random access memory with its inherent time delays in a manner that virtually eliminates the effect of any time delay in overall memory access throughput.
Claims17
A multi-port communications system data transfer service combined interrupt request/DMA request arbitrator, direct memory access controller and interrupt driven access controller for a bus inter-connected processor and memory system providing communications services, comprising:
- a communications port service request arbitration means connected to a plurality of communications ports and receiving therefrom a plurality of contemporaneous interrupt and/or DMA requests for data transfer service, said arbitration means having a means for identifying the highest priority service request from among said contemporaneous requests and means for issuing a channel identification therefor;
- a direct memory access control means connected to said arbitration means for receiving said channel identification and responsive thereto for issuing a direct memory access bus request to said processor;
- and
- a data buffer and a state control logic means, said state control logic means being connected to said processor and responsive to a receipt from said processor of a bus grant signal for causing issuance from said buffer to said processor of a direct memory access address identifying the memory location for reading or writing data;
- and
- an interrupt control means connected for receiving said channel identification from said arbitration means and responsive thereto for issuing interrupt signals to said processor;
- and
- said interrupt control means being responsive to the receipt of an interrupt acknowledgement signal from said processor for issuing a memory address vector for locating the start of an interrupt program for handling said interrupt.
An integrated multi-port direct memory access and interrupt arbitration and control means, comprising:
- a data transfer mode selector means for defining whether either the direct memory access or interrupt mode of data transfer service exists for each requesting port;
- a direct memory access transfer processor connected to said mode selection means and responsive thereto for performing a direct memory access mode data transfer at each requesting port defined as having said direct memory access mode of data transfer;
- an interrupt driven transfer controller connected to said mode selection means and responsive thereto for performing an interrupt mode data transfer at each requesting port defined as having said interrupt mode of data transfer.
Dependencies are inferred from the claim text.