US 4,714,994 A · Instruction prefetch buffer control

Abstract

An instruction prefetch buffer control (20) is provided for an instruction prefetch buffer array (10) which stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed. The instruction prefetch buffer control includes a register (201) for storing an instruction fetch pointer, this pointer being supplied to the buffer array (10) as a write pointer which points to the location in the array where a new word is to be written from main memory. A second register (205) stores an instruction execution pointer which is supplied to the buffer array (10) as a read pointer. A first adder (203) increments the first register to increment the instruction fetch pointer for sequential instructions and calculates a new instruction fetch pointer for branch instructions. A second adder (215) increments the second register to increment the instruction execution pointer for sequential instructions and calculates a new instruction execution pointer for branch instructions. Incrementing of the second register is variable depending on the length of the instruction. A third adder ( 221) is responsive to the output of the first adder and a branch target address to calculate whether the target instruction is contained in the array (10) and, if it is, causes the new instruction execution pointer calculated by the second adder (215) to be loaded into the second register (205).

Claims8

Dependent claims

A method of controlling an instruction prefetch buffer that stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed, said method comprising the steps of:

storing an instruction fetch pointer which is supplied to said buffer as a write pointer that points to the location where a new word is to be written into the buffer;
writting instructions into said buffer at the locations pointed to by said instruction fetch pointer;
storing an instruction execution pointer which is supplied to said buffer as a read pointer that points to the location from which an instruction is to be read from the buffer;
reading instructions from locations in the buffer pointed to by said instruction execution pointer;
decoding each instruction read from the buffer to determine if it is a branch or jump instrustion;
determining if a target instruction of a branch or jump instruction is within a range of instructions which may be stored in the buffer;
determining for those target instructions found to be within said range if the target instruction is in the buffer;
and
setting the instruction execution pointer to the location of the target instruction found to be in the buffer, said target instruction being either preceding or following a current instruction in the buffer.

6 more elements

An instruction prefetch buffer control for buffer means that stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed, said instruction prefetch buffer control comprising:

first register means for storing an instruction fetch pointer, said instruction fetch pointer being supplied to said buffer means by said first register means as a write pointer which points to the location where a new word is to be written into said buffer means;
second register means for storing an instruction execution pointer, said instruction execution pointer being supplied to said buffer means by said second register means as a read pointer which points to the location in said buffer means where a word is to be read from said buffer means;
decoding means for decoding an instruction read from said buffer means to determine if that instruction is a branch or jump instruction;
first adder means for incrementing said first register means to increment said instruction fetch pointer for sequential instructions, said first adder means calculating a new instruction fetch pointer for branch or jump instructions;
second adder means for incrementing said second register means to increment said instruction execution pointer for sequential instructions, said second adder means calculating a new instruction execution pointer for branch or jump instructions;
first logic means responsive to said decoding means for determining if a target instruction of a branch or jump instruction read from said buffer means is within a range of instructions which may be in said buffer means;
and
second logic means for determining if a target instruction found to be within said range is in said buffer means, said second logic means including third adder means responsive to said first adder an a branch target address to calculate whether the target instruction is contained in said buffer means and, if it is, causing the new instruction execution pointer calculated by said second adder means to be loaded into said second register means.

5 more elements

Dependencies are inferred from the claim text.

Instruction prefetch buffer control

Life of this patent

Instruction prefetch buffer control

Life of this patent

Abstract

Claims8