US 4,714,924 AGranted

Electronic clock tuning system

AssigneeETA Systems, Inc.

InventorJohn H. A. Ketzler

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Abstract

An electronic clock tuning system for a digital computer of the type including a plurality of major function circuit boards comprised of a plurality of gate arrays. A clock pulse train is produced by a master oscillator, and distributed to each major function circuit board by a master fanout. The clock pulse train is distributed throughout each major function circuit board by a local fanout. Each major function circuit board includes a plurality of electronic delay arrays, each of which distributes the clock pulse train to a group of gate arrays on the major function board, and delays the clock pulse train supplied to each gate array by one of a plurality of discrete delay periods. Each electronic delay array includes shift registers for serially receiving digital delay tuning codes and for producing digital delay select signals representative of discrete delay periods. Delay circuits on each electronic delay array are responsive to one of the shift registers, and delay the clock pulse trains supplied to the gate arrays by discrete delay periods represented by the digital delay select signals.

Claims15

Dependent claims

An electronic clock tuning system for distributing tuned clock pulse trains to integrated circuit gate arrays of a digital computer in which the gate arrays are organized into a plurality of regions on each of a plurality of major function circuit boards;

including:
master oscillator means for producing a clock pulse train;
master fanout means operatively connected to the master oscillator means for distributing the clock pulse train to each major function circuit board;
a plurality of local fanout means, each mounted with respect to one of the major function circuit boards and operatively connected to the master fanout means for distributing the clock pulse train to each region of the major function circuit board;
tuning code generator means for generating coarse and fine digital delay tuning codes, for each gate array, representative of desired discrete
a plurality of electronic delay means, each associated with and mounted with respect to a region of a major function circuit board and operatively connected to the local fanout means on the circuit board, for distributing the clock pulse train to each gate array of the region of the main function circuit board with which it is associated, and for delaying the distributed clock pulse train by one of a plurality of discrete delay periods, each electronic delay means comprising for each gate array of the region with which it is associated:
coarse delay select means coupled to the tuning code generator means for producing digital coarse delay select signals as a function of the coarse delay tuning codes;
fine delay select means coupled to the tuning code generator means for producing digital fine delay select signals as a function of the fine delay tuning codes;
coarse delay means coupled to the coarse delay select means for delaying the clock pulse train supplied to the gate array by discrete coarse delay periods represented by the coarse delay select signals;
and
fine delay means coupled to the coarse delay means and the fine delay select means for delaying the clock pulse train supplied to the gate array by discrete fine delay periods represented by the fine delay select signals.

8 more elements

master oscillator means for producing a clock pulse train;
local fanout means mounted with respect to the circuit board and operatively connected to the master oscillator means for distributing the clock pulse train to each region of the circuit board;
tuning code generator means for generating digital delay tuning codes, for each gate array of a region in a serial format, the tuning codes representative of desired discrete delay periods of the clock pulse trains distributed to the gate arrays of the region;
and
a plurality of electronic delay means, each associated with and mounted with respect to a region of the circuit board and operatively PG,24 connected to the local fanout means for distributing the clock pulse train to each gate array of the region with which it is associated, and for delaying the distributed clock pulse trains by one of a plurality of discrete delay periods, each electronic delay means comprising:
a plurality of delay shift register means, each associated with a gate array of the region, for receiving the digital delay tuning codes and for producing digital delay select signals representative of discrete delay periods in a parallel format, the delay shift register means for each region all being connected in series with one another and in series with the tuning code generator means;
and
a plurality of delay means each associated with and coupled to receive the delay select signals from one of the delay shift register means, for delaying the clock pulse trains supplied to the gate array with which it is associated by discrete delay periods represented by the digital delay select signals.

5 more elements

Dependencies are inferred from the claim text.