Differential amplifier having ratioed load devices

A method of providing a process insensitive differential amplifier having improved offset voltage compensation, comprising the steps of:

• providing a differential input pair of transistors for receiving differential input voltages;
• coupling a plurality of series-connected load transistors to each transistor of the input pair of transistors, the load transistors each having a control electrode connected together and to a first transistor of the input pair of transistors, each control electrode having a first predetermined control electrode width/length dimension to form a first composite predetermined control electrode dimension;
• and
• coupling an output stage to the load transistors, said output stage providing an output voltage of the differential amplifier and having a source transistor coupled in series with a sink transistor, said sink transistor implemented by a plurality of parallel-connected transistors, the parallel-connected transistors each having a control electrode connected together and to a second transistor of the input pair of transistors, each control electrode having a second predetermined control electrode width/length dimension to form a second composite predetermined control electrode dimension ratioed in a predetermined ratio with the first composite predetermined control electrode dimension.

A process insensitive differential amplifier having improved offset voltage correction, comprising:

• a first transistor of a first conductivity type having a first current electrode coupled to a power supply voltage, a second current electrode, and a control electrode for receiving a bias voltage;
• a second transistor of the first conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving a first input voltage, and a second current electrode;
• a third transistor of the first conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving a second input voltage, and a second current electrode for providing an output terminal;
• a first plurality of transistors of a second conductivity type coupled in series between the second current electrode of the second transistor and a second power supply voltage, each of said transistors of the first plurality having a control electrode connected together and to the second current electrode of the second transistor with a first predetermined control electrode dimension to form a first composite predetermined control electrode dimension;
• a second plurality of transistors of the second conductivity type coupled in series between the second current electrode of the third transistor and the second power supply voltage, said first plurality being equal in number to the second plurality, and each transistor of the second plurality having a control electrode connected together and to the second current electrode of the third transistor and having the first predetermined control electrode dimension to form the first composite predetermined control electrode dimension;
• and
• an output stage coupled to the output terminal, said output stage having a sink transistor comprising a third plurality of transistors of the second conducitvity type coupled in parallel, each of the transistors of said third plurality also having a control electrode with the substantailly equal first predetermined control electrode dimension to form a second composite predetermined control electrode dimension ratioed in a predetermined ratio with the first composite predetermined control electrode dimension.