Process for making junction field-effect transistors
AssigneeMassachusetts Institute of Technology
InventorsHong-Kyun Choi, Bor-Yeu Tsaur
Life of this patent
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Abstract
A self-aligned integrated JFET device is described wherein an oxide extension region and a doped polysilicon gate is used as part of a self-aligned mask to form drain and source regions. Asymmetric JFETs for power circuit applications can be made in accordance with the invention. Additionally, complementary enhancement mode JFETs can be made in accordance with the invention, for low power consumption and excellent radiation-hardened characteristics.
Claims21
A method of forming a junction field-effect transistor on a substrate comprising the steps of:
- (a) forming an island of silicon on, or in, said substrate;
- (b) doping said island with one type of conductivity dopant;
- (c) forming two closely spaced regions of opposite conductivity in said island extending to an upper surface of said island;
- (d) forming oxide extension regions over said opposite conductivity regions;
- (e) forming opposite conductivity regions on either side of said oxide extension regions and between said regions;
- (f) forming a silicon gate region of said one type conductivity over said oxide extension regions, and the opposite conductivity region therebetween, to form a shallow p-n junction adjacent the interface between the silicon gate region and the underlying region between the oxide extensions;
- and
- (g) forming source and drain regions of opposite conductivity at either side of the gate region using the oxide extension regions and gate region as a mask.
A method of forming an integrated junction field-effect device on a substrate comprising the steps of:
- (a) forming an isolated device region of substantially single crystal silicon on a substrate;
- (b) providing an impurity of one type conductivity in said device region;
- (c) forming two closely spaced regions of opposite conductivity in said device region at exposed surfaces thereof;
- (d) forming oxide extension regions over said opposite conductivity regions;
- (e) forming opposite conductivity regions on either side of said oxide extension regions and between said regions;
- (f) forming a polysilicon layer of said one type conductivity over said opposite conductivity regions and oxide extension regions;
- (g) selectively removing said polysilicon layer to leave a gate region extending over and between the oxide extension regions to form a shallow junction adjacent the interface between the gate region and the underlying opposite conductivity region between the oxide extension regions;
- and
- (h) forming source and drain regions of opposite conductivity at either side of the gate region using the oxide extension regions and gate region as a mask.
Dependencies are inferred from the claim text.