Single transistor electrically programmable memory device and method

An electrically erasable memory device having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a plurality of erase lines, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of storage sites comprises a single transistor including

• a source coupled to an associated one of the plurality of erase lines;
• a drain coupled to an associated one of the plurality of column address lines;
• a control gate coupled to an associated one of the plurality of row address lines;
• and
• a floating gate positioned between the gate and the source and drain;
• and further including
• means for injecting hot electrons onto the floating gate when the associated ones of the column address and row address lines are raised to a first predetermined potential above that of the associated one of the erase line;
• and
• means for inducing Fowler-Nordheim tunneling of electrons from the floating gate to the source when the associated erase line is raised to a second predetermined potential above the associated row address line.