US 4,694,326 AGranted

Digital phase locked loop stabilization circuitry including a secondary digital phase locked loop which may be locked at an indeterminate frequency

AssigneeRCA Corporation

InventorWalter H. Demmer

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Abstract

A digital television receiver includes a first phase locked loop which develops a sampling clock signal that is locked to the horizontal line synchronizing signals components of a composite video signal. A second digital phase locked loop is clocked by the sampling clock signal and develops a digital signal that is phase locked to the color burst signal. This signal is used as a regenerated color subcarrier signal to synchronously demodulate the chrominance components of the composite video signal into I and Q color difference signals. To compensate for frequency instabilities in the regenerated subcarrier signal caused by frequency instabilities in the line-locked clock signal, a third digital phase locked loop develops an oscillatory signal which is phase locked to a reference signal generated by a crystal controlled oscillator. Control signals from the third phase locked loop are applied to circuitry which develops control signal that is independent of the crystal frequency. This control signal is applied to the second phase locked loop to substantially compensate for frequency instabilities related to the clock signal. Since the control signal applied to the second phase locked loop is independent of the frequency of the control, there is no need for manual adjustment of the crystal oscillator.

Claims13

Dependent claims

In circuitry including a source of clock signal, the instantaneous frequency of which varies about a nominal clock frequency, and a first digital oscillator responsive to said clock signal and to a first frequency control signal for developing an output signal having a predetermined frequency wherein the variations in the frequency of said clock signal tend to cause corresponding variations in the frequency of said output signal, circuitry for substantially removing the variations in the frequency of said output signal comprising:

means for developing a further reference signal having a substantially invariant frequency;
a phase locked loop including:
a second digital oscillator responsive to said clock signal and to a second frequency control signal for providing an oscillatory signal having substantially the same frequency as said reference signal wherein the variations in the frequency of said clock signal tend to cause corresponding variations in the frequency of said oscillatory signal;
and
means coupled to said source of reference signal for developing said second frequency control signal being proportional to the difference in phase between said reference signal and said oscillatory signal and tending to compensate said phase locked loop for the variations in the frequency of said oscillatory signal that are related to said clock signal;
means responsive to said second frequency control signal for developing a standard frequency control value representing the value of said second frequency control signal when the frequency of said clock signal is substantially equal to said nominal clock frequency;
means for combining said standard frequency control value and said second frequency control signal to generate a correction signal representing the variations in the frequency of said clock signal with respect to said nominal clock frequency and being substantially independent of said further reference signal;
and
means coupled to said correction signal developing means for modifying said first frequency control signal by said correction signal to substantially remove frequency instabilites in said output signal corresponding to frequency instabilites in said clock signal.

6 more elements

Apparatus comprising:

a terminal for applying a clock signal the instantaneous frequency of which varies about a nominal clock frequency;
a digital oscillator responsive to said clock signal and to a first frequency control signal for developing an output signal having a predetermined frequency, wherein the variations in the frequency of said clock signal tend to cause corrsponding variations in the frequency of said output signal;
means for developing a reference signal having a substantially invariant frequency;
a phase locked loop including:
a discret time oscillator responsive to said clock signal and to a second frequency control signal for providing an oscillatory signal that has substantially the same frequency as said reference signal, wherein the variations in the frequency of said clock signal tend to cause corresponding variations in the frequency of the signal provided by said discrete time oscillator;
and
means including phase comparison means coupled to said source of reference signal and to said discrete time oscillator for developing said second frequency control signal representing the difference in phase between said reference signal and said oscillatory signal and tending to compensate said phase locked loop for the variations in the frequency of said oscillatory signal that are related to said clock signal;
means responsive to said second frequency control signal for developing a standard frequency control value representing the value of said second frequency control signal when the frequency of said clock signal is substantially equal to said nominal clock frequency;
means for combining said standard frequency control value and said second frequency control signal to generate a correction signal representing the variations in the frequency of said clock signal with respect to said nominal clock frequency and being substantially independent of said reference signal;
and
combining means coupled to said correction signal developing means for combining said first frequency control signal and said correction signal to produce a modified first frequency control signal for application to said digital oscillator to substantially remove the variations in the frequency of said output signal that are related to said clock signal.

8 more elements

Apparatus comprising:

a terminal for applying a clock signal which exhibits frequency instabilities;
a digital oscillator responsive to said clock signal and to a first frequency control signal for developing an output signal having a predetermined frequency, wherein the frequency instabilites in said clock signal tend to cause corresponding frequency instabilites in said output signal;
means for developing a reference signal having a substantially invariant frequency;
a phase locked loop including:
a discrete time oscillator responsive to said clock signal and to a second frequency control signal for providing an oscillatory signal that has substantially the same frequency as said reference signal, wherein the frequency instabilities in said clock signal tend to cause corresponding frequency instabilities in the signal provided by said discrete time oscillator;
and
means including phase comparison means coupled to said source of reference signal and to said discrete time oscillator for developing said second frequency control signal representing the difference in phase between said reference signal and said oscillatory signal and tending to compensate said phase locked loop for the frequency instabilities in said oscillatory signal that are related to said clock signal;
combining means, coupled to receive a correction signal, for combining said correction signal and said first frequency control signal to produce a modified first frequency control signal for application to said digital oscillator to substantially remove the variations in the frequency of said output signal that are related to said clock signal;
and
means for developing said correction signal including:
sample storage means having an input port coupled to receive said second frequency control signal and an output port and responsive to a sample storage control signal being in a predetermined state for storing selected samples of said second frequency control signal;
means coupled to said combining means for developing said sample storage control signal including means for changing the sample storage control signal to said predetermined state and means for comparing the signal provided by said combining means against a predetermined value and means for changing the sample storage control signal to a state other than said predetermined state when said modified first frequency control signal has a predetermined relationship to said predetermined value;
and
signal dividing means having a first input port coupled to receive said second frequency control signal, a second input port coupled to the output port of said sample storage means and an output port for providing said correction signal to said combining means.

11 more elements

A digital television signal processing system comprising:

an input terminal for applying composite video signals including horizontal line synchronizing signal components and chrominance signal components including a color reference burst signal component;
a first phase locked loop responsive to said composite video signals and having a predetermined loop time constant for generating a sampling clock signal that is locked in phase to said horizontal line synchronizing signal components, wherein the instantaneous frequency of said sampling clock signal varies about a nominal clock frequency;
a second digital phase locked loop, responsive to said clock signal and to said composite video signals and having a loop time constant that is substantially greater than that of the first phase locked loop for developing an output signal having substantially the same frequency as the color reference burst signal component of said composite video signals, wherein said output signal tends to exhibit variations in frequency that are related to the variations in the frequency of said clock signal;
means for developing a reference signal having a substantially invariant frequency;
a third phase locked loop, responsive to said reference signal and to said clock signal and having a loop time constant that is not significantly greater than that of said first phase locked loop, for developing an ocillatory signal that has substantially the same frequency as said reference signal and that tends to exhibit variations in frequency that are related to the variations in the frequency of said clock signal, wherein said third phase locked loop includes circuitry for developing a compensating control signal, proportional to the differences in frequency between said reference signal and said oscillatory signal said compensating control signal corresponding to the variations in the frequency of said clock signal, to condition said third phase locked loop to substantially compensate for the variations in the frequency of said oscillatory signal that are related to said clock signal;
means coupled to said third phase locked loop and responsive to said compensating control signal for developing a standard frequency control value representing the value of said compensating control signal when the frequency of said clock signal is substantially equal to said nominal clock frequency;
combining means for combining said standard frequency control value and said compensating control signal to generate a correction signal representing the variations in the frequency of said clock signal with respect to said nominal clock frequency, wherein said correction signal is substantially independent of said reference signal;
and
compensating means coupled to said second phase locked loop and responsive to said correction signal for substantially compensating said second phase locked loop for the variations in the frequency of said output signal which are related to said clock signal.

6 more elements

Dependencies are inferred from the claim text.