Comparator with cascaded latches

A comparator comprising:

• an amplifying stage having an input and an output;
• first means for selectively applying a reference signal to said input of said amplifying stage;
• second means for selectively applying an input signal to be sampled to said amplifying stage and for comparing said input signal with said reference signal and for producing a signal at the output of said amplifying stage indicative of the difference between said input signal and said reference signal;
• first and second latchable circuits, each one of said first and second circuits having an input and an output, each one of said first and second circuits being operable in either a first mode in which the circuit functions to receive data applied to its input or in a second mode as a regenerative latch;
• means for coupling the input of said first circuit to the output of said amplifying stage and means for coupling the output of said first circuit to the input of said second circuit;
• means coupled to said first and second circuits for operating said first circuit in said first mode and said second circuit in said second mode during one time interval and for operating said first circuit in said second mode and said second circuit in said first mode during a subsequent time interval;
• and
• a decoding means coupled to the output of said second circuit.