Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations

A data transmission station comprising:

• (a) a clock terminal;
• (b) a data terminal;
• (c) means for producing a clock signal at the clock terminal by allowing the clock terminal to assume a second voltage level for each of a series of periodic clock pulse intervals and by forcing the clock terminal to a first voltage level at all other times during production of the clock signal;
• (d) means for producing a start signal which indicates that the station is prepared to transmit data by allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;
• (e) means for producing a stop signal which indicates that the station has finished transmitting data by forcing the voltage level at the data terminal to the first voltage level during a first fraction of a clock pulse interval and then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval;
• and
• (f) means for transmitting binary data by forcing the voltage at the data terminal to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage at the data terminal to assume the second voltage level during an entire clock pulse interval to transmit a second data value.

A system for data transmission comprising:

• (A) at least two master transmitting stations which are capable of controlling data transmission, each comprising:
• (a) a clock terminal;
• (b) a data terminal;
• (c) a time slot generator which produces a periodic clock signal at the clock terminal by first forcing the clock terminal to a first voltage level for a first interval of predetermined duration, by then allowing the clock terminal to assume a second voltage level for a clock pulse interval of predetermined duration, and by then again forcing the clock terminal to the first voltage level;
• (d) means which detect the voltage level at the clock terminal and which cause the time slot generator to start the first interval whenever the voltage level at the clock terminal changes from the second voltage level to the first voltage level;
• (e) means for producing a start signal which indicates that the master station is prepared to control data transmission allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;
• (f) means for producing a stop signal which indicates that the master station is finished controlling data transmission by forcing the voltage level at the data terminal to the first voltage level during a first fraction of the clock pulse interval and by then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval;
• (g) means for transmitting binary data by forcing the voltage at the data terminal to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage at the data terminal to assume the second voltage level during an entire clock pulse interval to transmit a second data value;
• (B) at least one receiving station comprising a data terminal and a clock terminal;
• (C) a data bus which interconnects the data terminals of all of the stations;
• (D) a clock bus which interconnects the clock terminals of all of the stations;
• and
• (E) means which maintain the buses at the second voltage level in the absence of forcing by the stations.

A system for data transmission comprising:

• (A) at least two master transmitting stations which are capable of controlling data transmission, comprising each:
• (a) a clock terminal;
• (b) a data terminal;
• (c) means for producing a clock signal at the clock terminal by allowing the clock terminal to assume a second voltage level for each of a series of periodic clock pulse intervals and by forcing the clock terminal to a first voltage level at all other times during production of the clock signal;
• (d) means for producing a start signal which indicates that the master station is prepared to control data transmission by allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;
• (e) means for producing a stop signal which indicates that the master station has finished controlling data transmission by forcing the voltage level at the data terminal to the first voltage level during a first fraction of a clock pulse interval and then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval;
• and
• (f) means for transmitting binary data by forcing the voltage at the data terminal to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage at the data terminal to assume the second voltage level during an entire clock pulse interval to transmit a second data value;
• (B) at least one receiving station comprising a data terminal and a clock terminal;
• (C) a data bus which interconnects the data terminals of all of the stations;
• (D) a clock bus which interconnects the clock terminals of all the stations;
• and
• (E) means which maintain the buses at the second voltage level in the absence of forcing by the stations.

In a system for data transmission, the improvement comprising:

• (A) a master transmitting station which is capable of controlling data transmission, comprising:
• (a) a clock terminal;
• (b) a time slot generator which produces a periodic clock signal at the clock terminal by first forcing the clock terminal to a first voltage level for a first interval of predetermined duration, by then allowing the clock terminal to assume a second voltage level for a second interval of predetermined duration, and by then again forcing the clock terminal to the first voltage level;
• and
• (c) means which detect the voltage level at the clock terminal and which cause the time slot generator to start the first interval whenever the voltage level at the clock terminal changes from the second voltage level to the first voltage level;
• (B) at least one receiving station comprising a clock terminal;
• (C) a clock bus which interconnects the clock terminals of all of the stations;
• and
• (D) means which maintain the clock bus at the second voltage level in the absence of forcing by the stations.

A data tansmission station comprising:

• (a) a clock terminal;
• (b) a data terminal;
• (c) means for producing a clock signal at the clock terminal by allowing the clock terminal to assume a second voltage level for each of a series of periodic clock pulse intervals and by forcing the clock terminal to a first voltage level at all other times during production of the clock signal;
• (d) means for producing a start signal which indicates that the station is prepared to transmit data by allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;
• (e) means for producing a stop signal which indicates that the station is finished transmitting data by forcing the voltage level at the data terminal to the first voltage level during a first fraction of a clock pulse interval and by then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval;
• (f) means for transmitting binary data by forcing the voltage at the data terminal to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage at the data terminal to assume the second voltage level during an entire clock pulse interval to transmit a second data value;
• and
• (g) means for establishing priority if a plurality of interconnected stations simultaneously attempt to control data transmission which detect the voltage level at the data terminal and which cause the station to allow both the clock terminal and the data terminal to assume the second voltage level for at least a predetermined interval after detection of the first voltage level on the data terminal during a clock interval in which the station has allowed the data terminal to assume the second voltage level.

A method of data transmission on a data transmission system which comprises a plurality of stations, each station having a data terminal and a clock terminal, the data terminals of all stations being interconnected by a data bus and the clock terminals of all stations being interconnected by a clock bus, comprising:

• transmitting a clock signal from a first master station along the clock bus by allowing the clock terminal of the first master station to assume a second voltage level during each of a series of periodic clock pulse intervals and by forcing the clock terminal of the first master station to a first voltage level at all other times during transmission of the clock signal;
• transmitting a start signal, which indicates that the first master station is prepared to control data transmission, by allowing the data terminal of the first master station to assume a second voltage level during a first fraction of a clock pulse interval and then forcing the voltage level at the data terminal of the first master station to a first voltage level during said clock pulse interval;
• transmitting a stop signal which indicates that the first master station has finished controlling data transmission by forcing the voltage level at the data terminal of the first master station to the first voltage level during a first fraction of the clock pulse interval and by then allowing the voltage level at the data terminal of the first master station to transition to the second voltage level during the same clock pulse interval;
• and
• transmitting binary data by forcing the voltage level of a data terminal of a station to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage level at the data terminal of said station to assume the second voltage level during an entire clock pulse interval to transmit a second data value.

A communication system comprising:

• a first plurality of transmitting and receiving stations including at least one master station and at least one slave station;
• a data bus for transporting a series of data bits between at least one transmitting station and at least one receiving station;
• a clock bus for transporting a synchronizing clock signal in synchronism with each data bit;
• each bus further comprising logic means for forming a wired logic function between levels which denote a first and a second logic value respectively which are transmitted by the stations so that the level of the bus can be pulled to the first logic value by any station presenting a signal having the first logic value to the bus thereby masking any signal having the second logic value that may be presented to the bus;
• each transmitting station comprising data transmitting means which, in each bit cell of a selected bit cell sequence, present a respective data bit on the data bus for a period of time which covers the duration of the associated clock pulse, including the edges thereof;
• wherein each master station comprises:
• (a) clock transmitting means which generate a series of clock pulses, each having the second logic value, on the clock bus to define a series of bits cells;
• (b) means which form a first stop signal by forming a signal transition on the data bus from said first logic value to said second logic value, during the presence of a signal of the second logic value on the clock bus;
• (c) means which form a first start signal by forming a signal transition on the data bus from said second logic value to said first logic value during the presence of a signal of the second logic value on the clock bus;
• all non-master stations connected to the system comprising means for continuously presenting said second logic value to the clock bus and any non-transmitting station connected to the system comprising means for continuously presenting said second logic value to the data bus during said selected bit cell sequences.

Apparatus which operates as a master transmitter for data transmission comprising:

• a data terminal for communicating a series of data bits;
• a clock terminal for communicating a synchronizing clock signal, which defines a bit cell in synchronism with each data bit;
• wherein the terminals have a low output impedance for a first logic value locally presented on said terminals and the terminals have a substantially higher output impedance for a second logic value locally presented on said terminals;
• clock transmitting means which generate a clock pulse at the clock terminal which has the second logic value in each bit cell;
• data transmitting means which generate a respective data bit on the data terminal for a period of time which covers the duration of the associated clock pulse, including the edges thereof, in each bit cell of selected bit cell sequences;
• means which form a stop signal by forming a signal transition at the data terminal from said first to said second logic value during the generation of a signal of the second logic value at the clock terminal;
• and
• means which form a first start signal by forming a signal transition at the data terminal from said second logic value to said first logic value during generation of a signal of the second logic value on the clock terminal.

Apparatus which operates as a master receiver for data transmission comprising:

• a data terminal for communicating a series of data bits;
• a clock terminal for communicating a synchronizing clock signal, which defines a bit cell in synchronism with each data bit;
• wherein the terminals have a low output impedance for a first logic value locally presented on said terminals and the terminals have a substantially higher output impedance for the second logic value locally presented on said terminals;
• clock transmitting means which generate a clock pulse having the second logic value in each bit cell at the clock terminal;
• means for continuously generating a signal having said second logic value which is overridable by a lower impedance signal of said first logic value in each bit cell of selected bit cell sequences at the data terminal;
• means which form a stop signal by forming a signal transition at the data terminal from said first to said second logic value during the generation of a signal of the second logic value on the clock terminal;
• means which form a start signal by forming a signal transition at the data terminal from said second logic value to said first logic value during presentation of a signal of the second logic value on the clock terminal.

Apparatus which operates as a slave transmitter for data transmission comprising:

• a data terminal for communicating a series of data bits;
• a clock terminal for communicating for a synchronizing clock signal which defines a bit cell in synchronism with each data bit;
• wherein the data terminal has a low output impedance for a first logic value locally presented on said data terminal and the data terminal has a substantially higher output impedance for a second logic value locally presented on said data terminal;
• and
• data transmitting means which generate a respective data bit at the data terminal for a period of time which covers the duration of a second logic value clock pulse signal, including the edges thereof, which is received at the clock terminal in each bit cell of selected bit cell sequences.

Apparatus which operates as a slave receiver for data transmission comprising:

• a data terminal for receiving a series of data bits;
• a clock terminal for receiving a synchronizing clock signal which defines a bit cell in synchronism therewith for each data bit;
• means which continuously generate a second logic value at the clock terminal which is overridable by a lower impedance signal of a first logic value, during each bit cell of selected bit cell sequences;
• means which continuously generate said second logic value at the data terminal which is overridable by a lower impedance signal of said first logic value, in each bit cell of said bit cell sequences;
• means which send an acknowledge bit which directly follows said bit cell sequence;
• and
• means which selectively control a transition of said apparatus to a non-receiver condition in response to an eighth bit of an eight bit data sequence which is received at the data terminal.