Bit processing utilizing a row and column ladder sequence
AssigneeHitachi, Ltd.
InventorsHiromasa Yamaoka, Tadashi Okamoto, Yuzaburo Iwasa, Kouichi Kimura
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Abstract
A relay ladder sequence circuitry having i columns and j rows is divided into a plurality of sections each having a predetermined number of rows, and the bit informations are processed in a parallel manner in the rows of the sections. More specifically, the program in accordance with the sequence ladder construction is memorized and are successively read out as the addresses of the program are appointed. The signals of relay contacts as the bit information are processed for each line in accordance with the read out program, so that a high processing speed is attained.
Claims8
A method for processing a sequence control for a ladder sequence consisting of constituent elements including input contacts and output devices functionally arranged in i columns and j rows, comprising the steps of:
- (a) dividing said i columns out of said constituent elements of i columns and j rows into blocks of columns each including a predetermined plural number of columns;
- (b) storing an instruction in a memory unit for each row in said block of columns, said instruction being composed of a control portion including a bit indicating start of sequence and a bit for discriminating whether relay contact information is to be taken in or issued, a first operation code portion indicating whether input contacts of the ladder sequence are normally-OFF contacts or normally-ON contacts, a second operation code portion including bits for discriminating the presence or absence of connection between the adjacent columns, and an input/output address portion indicating addresses of the input contacts and output devices;
- (c) obtaining bit information corresponding to the ON/OFF condition of the input contacts for each row of said block of columns;
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- (d) processing the bit information for each row in said block of columns with a clock signal in accordance with said instruction stored in said memory means.
In a central processor wherein a ladder sequence consisting of constituent elements including input contacts and output devices functionally arranged in i columns and j rows, said i columns being divided into blocks of columns each including a predetermined plural number of columns, and wherein arithmetic processing is run in accordance with an instruction stored in a memory unit with an ON/OFF status signal for each row of said block of columns as input data, and the resultant values are issued a central processor for sequence control comprising:
- (a) a program memory for storing therein an arithmetic processing instruction and for issuing said instruction in accordance with a read-out address;
- (b) input signal inverting means for processing bit information for a row in one block of columns with a clock signal to determine whether the input data bits are issued after inversion or directly, in accordance with a first operation code in the instruction read out from said program memory for said input data, said first operation code including bits for discriminating whether the constituent elements corresponding to said input data are normally-OFF contacts or normally-ON contacts;
- (c) logical product means for effecting a logical product operation with an output signal from said input signal inverting means and the content of an accumulator being both as input signals;
- (d) a column to column bit arithmetic unit for effecting an operation between bits in the adjacent columns for respective bits of the output data from said logical product means, in accordance with a second operation code in said read-out arithmetic processing instruction, said second operation code including bits for discriminating the presence or absence of logical sum (OR) connection between the constituent elements corresponding to said input data;
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- (e) an accumulator for latching an output signal from said column to column bit arithmetic unit.
Dependencies are inferred from the claim text.