Single bit storage and retrieval with transition intelligence

A memory shift register operable in response to write commands signaled on data and address buses from a central processor and comprising, in combination,

• a first addressable memory having a plurality of address inputs, a plurality of data terminals, and a read/write control terminal,
• a second addressabe memory having a plurality of address inputs connected to corresponding address inputs of the first memory, a plurality of data terminals, and a read/write control terminal connected to the read/write terminal of the first memory, and
• a latch having a clock input and data inputs connected to the data terminals of the first memory and having data outputs connected to the data terminals of the second memory, and
• clocking means responsive to a write command signaled on said buses for generating a cyclic read/write signal to the read/write terminals of the memories and generating a clock signal to the latch so that during a single cycle of said read/write signal data are successively (a) read from an addressed location of the first memory, (2) clocked into the latch, and then (3) written from the latch into the second memory at a corresponding memory location.

In a digital computer system having a central processor and several boards connected to a computer bus having an address bus and a data bus, the boards including at least one memory board and a single-bit signal input board,

• a memory processor board comprising, in combination
• (a) present scan memory means for receiving multiple bit words of data during a memory write operation by the central processor, said present scan memory means having address inputs receiving address signals from said address bus and data terminals for receiving data from said data bus for storage and for later asserting the stored data when the stored data are addressed,
• (b) past scan memory means for receiving at corresponding addresses words of original data transferred from the present scan memory before the present scan memory receives corresponding new words of data from the central processor unit, said past scan memory means having address inputs receiving address signals from said address bus and data terminals for receiving said data for storage and for later asserting the stored data when the stored data are addressed,
• (c) logic processor means interconnecting said present and past memories and said data bus for
• (i) receiving from said data terminals of the present scan memory means and the past scan memory means said data addressed during a single read cycle executed by the central processor, the two memories asserting on their said data terminals stored values read from respective corresponding memory locations addressed in part by the central processor,
• (ii) performing one of a plurality of logical operations including detecting transitions in corresponding bits by combining the values asserted on the data terminals of the present scan memory with the values asserted on the data terminals of the past scan memory, and
• (iii) placing on said data bus for return to said central processor unit during such read cycle either (1) a selected bit of the value asserted on the data terminals of said present scan memory means, (2) the complement of said last-mentioned selected bit, or (3) an indication of a transition in corresponding selected bit places of the values asserted on the data terminals of said present scan and past scan memories,
• said means (c) including means responsive to signals asserted on said address bus during said read cycle for selecting one of said actions (1) to (3) depending on whether the address bus signals are within a first, second, or third predetermined range of addresses, respectively.