# US 4,688,097 A · D.C.-coupled video clamping circuit

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- Number: US 4,688,097 A
- Document ID: US4688097A
- Status: Granted
- Kind: A
- Application number: 06/924,880
- Filed: 1986-10-30
- Granted: 1987-08-18
- Earliest claimed: 1986-10-30
- Assignees: Jerrold Electronics Corporation
- Inventors: Wen T. Lin
- Web page: https://patentgrep.com/patent/US4688097A

## CPC

- H04N 5/18: by means of "clamp" circuit operated by switching circuit
- H04N 7/1713: {by modifying synchronisation signals}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A d.c.-coupled video clamping circuit is disclosed for operation with normal video signals and sync suppressed scrambled video signals. For receiving normal video signals, a feedback path detects variations in sync tip level from a reference level and applies a corresponding control voltage to a d.c. signal amplifier, thereby to clamp and maintain the sync tip at a fixed (black) level. For receiving sync suppressed scrambled video signals, the feedback path is disabled and a fixed reference voltage is applied to the d.c. signal amplifier.

## Claims

### Claim 1

A d.c.-coupled video clamping circuit comprising an input terminal , a d.c. signal amplifier having a first input for receiving normal or scrambled video signals coupled to said input terminal; feedback means connected to the output of said signal amplifier, said feedback means including means for detecting the sync tip level of a normal video signal and an error amplifier coupled to the output of said detecting means for producing an error signal representative of variations in the sync tip level from a desired reference level; and control means effective when in a first condition, when it is desired to receive a normal video signal, to apply said error signal to a second input of said signal amplifier, and effective when in a second condition, when it is desired to receive a scrambled video signal, to connect a reference voltage to said second input of said signal amplifier.

### Claim 2 (depends on 1)

The clamping circuit of claim 1, further comprising an impedance buffer interposed between the output of said detecting means and the input of said error amplifier.

### Claim 3 (depends on 1)

The d.c. clamping circuit of claim 1, in which said control means comprises a switch operable between said first and second conditions.