Weighted random pattern testing apparatus and method

An improvement in the method of testing of a complex integrated device having a LSSD shift register and accessible fewer input and output teriminals than the number of internally interconnected logic circuit elements coupled thereto which renders the elements inaccessible for discrete direct testing comprising the steps of:

• A. producing a pseudo random pattern containing one element for each accessible input terminal and inaccessible circuit element of the device to be tested;
• B. loading a portion of said pattern into the LSSD shift register of the device to be tested;
• C. applying a portion of said pattern to the accessible input terminals of the device under test;
• D. causing the device to operate in response to the inputs at the accessible input terminals and the data in the LSSD shift register;
• E. gating the signals from the logic circuit elements in the device under test into the LSSD shift register;
• F. unloading data from the LSSD shift register;
• and
• G. comparing the unloaded data with the precalculated data for a known good device to determine if the device under test failed;
• a portion of said pseudo random pattern being operative to modify said loading of the LSSD shift register, said unloading of said LSSD shift register or the gating of patterns from the LSSD shift register to the inaccessible logic elements in the device under test, thereby providing a means for detecting all potential stuck faults resident in the LSSD combinational networks as well as a means for detecting faults in and amongst the LSSD shift clocks, the system clocks, and associated gating networks.