US 4,683,645 AGranted

Process of fabricating MOS devices having shallow source and drain junctions

AssigneeNorthern Telecom Limited

InventorsHussein M. Naguib, Iain D. Calder, Vu Q. Ho, Abdalla A. Naem

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Abstract

In a metal oxide semiconductor field effect transistor fabrication process, refractory metal is deposited over designated source and drain areas within a silicon substrate. Refractory metal and silicon at the interface is then mixed by ion implantation of a heavy neutral ion species such as germanium. To minimize source/drain junction depth, the source and drain locations can be subjected to bombardment by a lighter ion such as silicon which amorphizes silicon to a predetermined depth under the designated source and drain regions and so substantially confines dopant diffusion to the silicon amorphized region. To render the source and drain of desired conductivity type, an ion implantation of a non-neutral ion is then performed.

Claims3

Dependent claims

A process for the fabrication of an MOS semiconductor device comprising:

forming on a silicon substrate regions of field oxide;
forming at a region not occupied by field oxide a gate oxide layer;
forming a device gate over a region of said gate oxide layer;
designating source and drain areas and removing gate oxide at said source and drain areas;
depositing a refractory metal on the silicon substrate at said source and drain regions;
implanting germanium ions at the source and drain areas to mix silicon and the refractory metal at an interface therebetween;
implanting silicon ions at the source and drain areas to cause amorphization of the silicon to a predetermined depth;
and
implanting dopant ions of a predetermined conductivity type at the source and drain areas whereby to render said areas of said type.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/813,232Filed 24 Dec 1985
Priority: CA 48587428 Jun 1985
Granted: 4 Aug 1987
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10P 30/204
Characterised by the semiconductor materials: into Group IV semiconductors
H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10D 64/0112
To Group IV semiconductors: using conductive layers comprising silicides
H10P 30/208
Into semiconductor materials, e.g. for doping: of electrically inactive species