Switching power supply with automatic power factor correction

A method for controlling power factor in switching power supplies, comprising the steps of:

• rectifying line current;
• alternately switching an inductor from a first position in parallel with said rectifier such that said inductor stores rectified line current to a second position in series with said rectifier and a load such that said inductor discharges said stored current into said load, said switching including the substeps of:
• (a) placing said inductor in said first position to charge said inductor with said rectified line current;
• (b) sensing the voltage across said load;
• (c) selecting a first time interval in response to the voltage across said load;
• (d) placing said inductor in said second position at the end of said first time interval;
• (e) sensing the discharge current through said inductor;
• (f) selecting a second time interval measured from the end of the first time interval to the point where the discharge current through said inductor is approximately zero;
• (g) sensing the voltage across said load;
• (h) selecting a second time interval extension in response to the voltage across said load;
• (i) placing said inductor in said first position at the end of said second time interval increased by said second time interval extension, if any;
• and
• (j) repeating steps (a) through (i).

A switching power supply for producing DC voltage capable of operating from either DC or AC supply lines having a wide variation of voltage and frequency with automatic power factor correction, comprising:

• line connection means for connecting to a power grid and for receiving line current;
• first rectifier means connected to said line connection means having first and second output terminals for producing rectified line current;
• inductor means for charging said rectified line current and for discharging said charged rectified line current having a first inductor terminal connected to said first output terminal of said first rectifier means and having a second inductor terminal;
• switching transistor means for operating in a first mode to connect said second inductor terminal to said second output terminal of said first rectifier means so that said inductor means charges said rectified line current and for operating in a second mode to disconnect said second inductor terminal from said second output terminal of said first rectifier means so that said charged rectified line current is discharged from said inductor;
• second rectifier means connected to said second inductor terminal for receiving said discharged rectified line current and for producing rectified inductor current;
• storage capacitor means having a first terminal connected to said second rectifier means for receiving said rectified inductor current and having a second terminal connected to said second output terminal of said first rectifier means;
• first DC output terminal connected to said first terminal of said storage capacitor means and second DC output terminal connected to said second output terminal of said first rectifier means;
• and
• control circuit connected to said switching transistor means, said second terminal of said first rectifier means, said second terminal of said inductor means, and said first terminal of said storage capacitor means for alternately placing said switching means in said first mode and said second mode, which comprises:
• on-time amplifier means for sensing the voltage across said storage capacitor and for controlling within preset limits a first time interval responsive to the voltage across said storage capacitor;
• reset detect means for sensing when said rectified inductor current through said second rectifier means is approximately zero and for controlling within preset limits a second time interval;
• off-time amplifier means for sensing the voltage on said storage capacitor and for extending said second time interval in response to approximately no-load conditions on said DC outputs;
• and
• clock circuit means for producing a high-frequency clock signal comprised of an alternating sequence of said first time interval followed by said second time interval so that said first time interval operates to place said switching transistor means in said first mode and said second time interval operates to place said switching transistor means in said second mode.