Logarithmic arithmetic logic unit

In a digital signal processing system, a logarithmic arithmetic logic unit for receiving first and second operands and implementing predetermined alogrithms, comprsing:

• first calculating means for selectively receiving the frist and second operands, each operand being in a logarithmic number representation, and for either multiplying or dividing said operands by effecting an addition or subtraction, respectively, of said first and second operands to provide an intermediate resultant operand at an output, said first calcualting means having a zero value operand detector for detecting when either the first or second operand has a quantized zero logarithmic value and having zero force means for outputting a quantized zero value without effecting said addition or subtraction, thereby minimizing quantization error;
• and
• second calculating means having a first input coupled to the output of the first calcualting means for receiving said intermediate resultant operand, and a second input for selectively receiving a third operand in a logarithmic number representation, said second calculating means selectively effecting a subtraction or addition of the intermediate resultant operand with the third operand to provide a final resultant operand in an logarithmic number representation, said second calculating means having bypass means for selectively directly outputting a predetermined one of the intermediate resultant operand or the third operand without effecting an addition or subtraction, said selective coupling being effected without use of a bypass path external to the second calculating means.