Integrated circuit chip carrier

A leadless chip carrier for protectively housing an integrated circuit chip and for electrically connecting the chip to external circuts on a circuit board, said chip carrier comprising:

• a body having an upper and lower surface and including a die attachment site;
• first contact pads;
• a slot formed in the lower surface of said body and extending through substantially the full thickness thereof, said slot disposed generally about a periphery of the body to define a laterally spaced sidewall connected to the body by a relatively thin connecting region;
• second contact pads disposed on said lower surface radially outwardly of the slot;
• electrical connections disposed on said connecting region and said sidewall of the carrier for connecting the first and second contact pads;
• wherein
• the relatively thin connecting region between said sidewall and said body is elastically deformable so that, in use, thermally induced strains of the chip carrier relative to the circuit board are accommodated by the connecting region.

A leadless chip carrier comprising:

• a one-piece structure having a central recess for receiving and protectively mounting an integrated circuit die;
• said structure having at least one interior wall portion and including at least one pair of spaced-apart sidewalls disposed at an edge of said structure, said spaced-apart sidewalls having a predetermined height and having an outer peripheral wall portion and an inner peripheral wall portion, said inner peripheral wall portion being laterally spaced apart from said interior wall portion of said structure,
• an integral thin elastically deformable link portion having a thickness substantially less than said predetermined height, said link portion interconnecting said spaced-apart sidewalls and said interior wall portion of the one piece structure, said link portion being disposed near a first upper carrier surface;
• said link portion, said spaced-apart sidewalls and said interior wall portion defining a slot;
• plural first conductive pads disposed for electrical connection to an integrated circuit ship mounted in said recess;
• and
• a plurality of second conductive pads disposed on an outermost sidewall and electrically connected along an outside of the outermost sidewall to respective ones of said first pads, said seconds pads being disposed near a second lower carrier surface remote from said link and being disposed for electrical connection to external circuits via said outermost sidewall and its associated link portion so as to reduce thermally induced stresses between the chip carrier and such connected external circuits.