Time-slot addressed, system keyed multiplex device

A remotely addressed terminal for a multiplex system of the type comprising a master controller which includes means for generating a series of clock pulses on a timing signal bus and means for transmitting data between a data bus and the controller, said terminal comprising:

• first means, coupled to the timing bus, for maintaining a count of individual clock pulses in sets, each clock pulse in each set designating a respective time slot;
• second means for counting the sets of clock pulses to form an address count;
• means for storing an address;
• interface means for transmitting a plurality of data signals between the data bus and the terminal, each of said data signals associated with a respective one of the time slots;
• means, included in the interface means, for selecting the data signal corresponding to the count of the first means;
• third means, responsive to the second means and the stored address, for causing the interface means to transmit the selected data signal between the data bus and the terminal during the respective time slot when the stored address corresponds to the address count;
• means, responsive to the clock pulses, for generating a reset signal when the time interval between successive clock pulses exceeds a selected value;
• and
• means for resetting the address count in response to the reset signal.

A remotely addressed terminal for a multiplex system of the type comprising a master controller which includes means for generating a series of clock pulses on a timing bus and means for inserting data signals on and monitoring data signals from a data bus, said terminal comprising:

• means, coupled to the timing bus, for counting clock pulses to generate a count;
• means, responsive to the clock pulses, for generating a reset signal when the time interval between successive clock pulses exceeds a selected value;
• means for resetting the count in response to the reset signal;
• means for storing a terminal address;
• means, responsive to the count and the terminal address, for detecting an address time when the count corresponds to the terminal address;
• means for detecting a first clock pulse which follows the address time by a first predetermined number of clock pulses;
• means for detecting a second clock pulse which follows the address time by a second predetermined number of clock pulses;
• means for gating a first selected one of the data signals from the data bus during a first time slot defined by the first clock pulse;
• and
• means for gating a second selected one of the data signals onto the data bus during a second time slot defined by the second clock pulse.