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US 4,682,057 AGranted
Circuit design technique to prevent current hogging when minimizing interconnect stripes by paralleling STL or ISL gate inputs
AssigneeHarris Corporation
InventorBrent R. Doyle
Life of this patent
Estimating the term…
Abstract
An STL or ISL logic circuit comprising a plurality of single-input, multiple-output logic gates is provided. Each of these gates has a current source and a transistor including a base, emitter and multiple Schottky diode-to-collector contacts. The bases of the logic gate transistors are tied together to minimize metal interconnect stripes when a fanout greater than that of one gate is needed. Current hogging is reduced by an ohmic collector contact with connects the collector of each transistor together.
Claims10
A logic circuit, comprising:
- a plurality of single-input, multiple-output logic gates each having a transistor including a base, emitter and collector, said single-input being applied to said base of said transistor, said multiple-outputs being taken from said collector of said transistor through Schottky diodes, said collector having an ohmic collector contact, said bases of said plurality of transistors being connected together and driven by a current source means, said emitters of said plurality of transistors being connected to a common potential node;
- and
- contact means interconnecting said ohmic collector contacts of said plurality of gates for reducing current hogging between the bsaes of said transistors when said logic gates have unequal load currents drawn by said multiple outputs.
A logic circuit, comprising:
- a plurality of single-input, multiple-output logic gates each having a transistor including a base, emitter and collector, said single-input being applied to said base of said transistor, said multiple-outputs being taken from said collector of said transistor through Schottky diodes, said collector having an ohmic collector contact, said bases of said plurality of transistor being connected together and driven by a current source means, said emitters of said plurality of transistors being connected to a common potential node;
- and
- contact means interconnecting said ohmic collector contacts for balancing the collector currents of said transistors irrespective of the current loading on said gates.
Dependencies are inferred from the claim text.