Low impedance package for integrated circuit die

A low inductive impedance dual in-line package for an integrated circuit chip or die comprising:

• a lead frame (120) formed with a central opening (160) and a plurality of electrically active lead fingers (122, 124, 125) extending radially at the perimeter of the central opening (160) substantially in a common plane of the lead frame, said lead frame (120) formed without a die attach paddle in the central opening and without paddle supports, said electrically active lead fingers including a ground lead finger (124) formed with first ground tab means (123) electrically continuous with the ground lead finger (124), said lead frame also formed with a plurality of first spacing tab means (152, 154, 155) isolated from the electrically active lead fingers so that the plurality of first spacing tab means (152, 154, 155) are rendered electrically inactive upon final trimming and forming of the package;
• a ground plate (140) forming a die attach plane parallel with and spaced from the common plane of the lead frame (120) for supporting an integrated circuit die on the side of the ground plate facing the lead frame and for imaging signal fields of the electrically active lead fingers in the ground plate, said ground plate being substantially coextensive in area with the common plane of the lead frame, said ground plate (140) formed with a plurality of second spacing tab means (142, 144, 145) corresponding to the respective plurality of first spacing tab means (152, 154, 155) on the lead frame (120), said first and second spacing tab means being joined to support the lead frame (120) and ground plate (140) in spaced apart coplanar relationship, said ground plate (140) also formed with a second ground tab means (146) complementary with the first ground tab means (123) on the ground lead finger (124) of the lead frame (1200, said first (123) and second(146) ground tab means being electrically joined for electrical contact between the ground lead finger (124) and ground plate (140) so that the ground lead finger and ground plate provide parallel coupled ground current paths thereby providing a ground lead with planar configuration to minimize inductive impedance to ground current and to minimize cross coupling between the electrically active lead fingers of the lead frame;
• and a dielectric layer formed between the lead frame and ground plate.

An improved lead frame (20, 120) for low inductance dual in-line packaging of an integrated circuit die, said improved lead frame having lead frame dam means (62, 162) along the sides of the lead frame and rail means (164) at the ends of the lead frame for supporting a plurality of lead fingers, a plurality of electrically active lead fingers (22, 24, 25;

• 122, 124, 125) supported by said dam means (62, 162) and rail means (164) and comprising a power lead finger (22, 122), a ground lead finger (24, 124), and a plurality of signal lead fingers (25, 125), said lead frame (20, 120)formed with a central opening (60, 160) with said lead fingers extending generally radially in a common plane at the perimeter of said central opening, and a plurality of pins or leads (26, 126) supported by the lead frame dam means (62, 162) correspomding to the respective lead fingers, wherein the improvement comprises:
• said lead frame (20, 120) being formed without a die attach paddle in the central opening of the lead frame and without die attach paddle supports;
• said power lead finger (22, 122) and ground lead finger (24, 124) being formed at least 2.5 times wider than the signal lead fingers (25,125) along a portion of the respective lengths of said lead fingers thereby reducing inductive impedance to power current and ground current;
• said ground lead finger (24, 124) being formed with first ground tab means (23, 123) electrically continuous with the ground lead finger (24, 124) for electrical contact with a ground coupling.