Data communication system and method and communication controller and method therefor, having a data/clock synchronizer and method

A multinode synchronous serial data closed loop communication system, comprising

• a plurality of nodes, including at least one synchronous dual function master/slave loop node, connected in a closed serial-data sequential synchronous node-to-node communication loop,
• each of said dual function master/slave nodes having the dual capability of selectively acting as either a loop master node providing a single loop time base or master clock for synchronous serial data sequential communication between each of said dual function master/slave loop nodes and each of the other of said dual function master/slave nodes, or as a slave node acting to slave in synchronism with said master clock provided by a single selected one of said dual function maste/slave nodes which is acting as the instant loop master node,
• each of said dual function master/slave nodes having loop master/slave select means responsive to detection of absence of an instant active loop master node on the loop, to effect assumption of loop master node status by each such dual function master/slave node,
• each of said dual function master/slave nodes having means for actuating the respective said master/slave select means to master-select mode after passage of a different time period after said detection of absence of an instant active loop master node on the loop, as compared to the corresponding said time period for all others of said dual function master/slave nodes.

A multinode synchronous serial data closed loop communication system, comprising,

• a plurality of nodes, including at least two synchronous dual function master/slave loop nodes, connected in a closed serial-data sequential synchronous node-to-node communication loop,
• each of said dual function master/slave nodes having the dual capability of selectively acting as either a loop master node providing a single loop time base or master clock for synchronous serial data sequential communication between each of said dual function master/slave loop nodes and each of the other of said dual function master/slave nodes, or as a slave node acting to slave in synchronism with said master clock provided by a single electled one of said dual function master/slave nodes which is acting as the instant loop master node,
• each of said dual function master/slave nodes having a selectively loop-time-base-forming master clock, and master clock receive data synchronizing means for synchronizing received data with its respective said selectively loop-time-base-forming master clock,
• said master clock receive data synchronizing means including
• phase-shifted-data-providing means for providing a selectively phase shifted form of data received at its respective said dual function master/slave node, as a function of the phase difference between a form of said received data and said selectively loop-time-base-forming master clock at the respective said dual function master/slave node, by an amount sufficient to enable effective sampling of said selectively phase shifted form of receive data by said selectively loop-time-base-forming master clock at the respective said dual function master/slave node.

A multinode serial data sequential node-to-node synchronous communication system, comprising

• a plurality of nodes interconnected in a closed sequential node-to-node synchronous serial data communication loop,
• one of said nodes having means for generating loop-time-base-forming master clock, and having the capacity of acting as the loop master node furnishing loop timing base or master clock source for data on said loop, while the other sid nodes act as slave nodes slaving to said loop time base,
• said one node having absolute phase synchronizing means for absolute phase synchronizing of data received by it from the loop with its own said master clock,
• said absolute phase synchronizing means including phase-shifted-data-providing means for providing a selectively phase-shifted form of data received at the respective said one node, as a function of the phase differences between a form of said received data and said loop-time-base-forming master clock at said one node, by an amount sufficient to enable effective sampling of said selectively phase-shifted form of receive data by said loop-time-base-forming master clock at said one node.

A multinode serial data sequential node-to-node synchronous communication system, comprising

• a plurality of synchronous dual function master/slave nodes interconnected in a closed sequential node-to-node synchronous serial data communication loop,
• each of said dual function master/slave nodes having means for generating selectively loop-time-base-forming master clock, and having the dual capacity of acting as either the loop master node furnishing loop timing base or master clock source for data on said loop, or as a slave node slaving to said loop time base,
• each of said dual function master/slave nodes having absolute phase synchronizing means for absolute phase synchronizing of data received by it from the loop with its own said master clock,
• said absolute phase synchronizing means including phase-shifted data providing means for providing a selectively phase-shifted form of data received at its respective said dual function master/slave node, as a function of the phase differences between a form of said received data and the said selectively loop-time-base-forming master clock at the respective said dual function master/slave node, by an amount sufficient to enable effective sampling of said selectively phase-shifted form of receive data by said selectively loop-time-base-forming master clock at the respective said dual function master/slave node.

An absolute phase synchronizer for synchronizing data received at one node of a multinode synchronous loop communication system, with a loop-time-base or master clock at said one node, and which said one node has clock recovery means and means for forming recovered clock receive data, said absolute phase synchronizer comprising

• means for comparing the phase of recovered clock relative to said master clock,
• coarse phase shifting means for coarse phase shifting of the phase of received data as a function of the result of said comparing, by an amount enabling effective sampling of received data by said master clock,
• sampling means for sampling said coarse phase shifted received data to thereby form master clock-sampled receive data in absolute phase synchronization with said master clock,
• said coarse phase-shifting means comprising:
• a shift register clocked at a rate which is a selected multiple of the rate of said recovered clock, which shift register has said recovered clock receive data as its input for shifting thereof, and has multiple phase-shifted outputs, each of which outputs represents said recovered clock receive data inputted thereto, shifted by a given phase which is a function of said selected multiple, and of the shift position of each of the respective shift register outputs,
• and means for selecting one of said multiple phase-shifted outputs of said shift register as a function of the phase relationship deteced by said phase-comparing means, to thereby enable effective sampling of said selected phase-shifted output by said master clock to thereby enable master clock receive data to be formed, in absolute phase synchronism with said master clock.

Absolute phase synchronizing means for phase synchronizing binary data with a master binary clock which said binary data has effectively the frequency of said master clock but which may not be in phase with said master clock comprising:

• means for forming a data-synchronized binary clock in synchronism with said binary data,
• phase-comparing means for comparing the phase of said data-synchronized binary clock with the phase of said master clock,
• coarse phase-shifting means for forming coarse phase-shifted data whose phase is shifted by a phase angle which based on the result of said comparing is an amount enabling effective sampling of said coarse phase-shifted data by said master clock,
• and means for sampling said coarse phase-shifted data with master clock to form master clock-sampled received data in absolute phase synchronization with said master clock.

For use in a multinode data communication system in which data is serially passed from node to node, and in which a node has serial-to-parallel/parallel-to-serial data conversion means requiring a clock in synchronization with received and transmitted serial data processed by said data conversion means, the improvement of a composite master/slave node data/clock synchronizer capable of operating in either a master or a slave mode, comprising,

• clock recovery means for recovering clock from received data and for sampling received data with said recovered clock to thereby form recovered clock-sampled received data in both phase and frequency synchronization with said recovered clock,
• master clock means for generating a master clock,
• means for comparing the phase of recovered clock relative to said master clock,
• coarse phase shifting means for coarse phase-shifting of the phase of received data as a function of the result of said comparing, by an amount enabling effective sampling of received data by said master clock,
• sampling means for sampling said coarse phase-shifting received data to thereby form master clock-sampled received data in absolute phase synchronization with said master clock,
• and means for selecting one of said master clock or said recovered clock as an output for application as an input to said data conversion means and for concomitantly selecting the associated said master clock-sampled received data or said recovered clock-sampled received data as an output for application as an input to said data conversion means.

For use in a multinode data communication system in which data is serially passed from node to node, and in which a node has serial-to-parallel/parallel-to-serial data conversion means requiring a clock in synchronization with received and transmitted serial data processed by said data conversion means, the improvement of a composite master/slave node data/clock synchronizer capable of operating in either a master or a slave mode, comprising

• clock recovery means for recovering clock from received data and for sampling received data with said recovered clock to thereby form recovered clock-sampled received data in both phase and frequency synchronization with said recovered clock,
• master clock means for generating a master clock,
• means for comparing the phase of recovered clock relative to said master clock,
• coarse phase-shifting means for coarse phase-shifting of the phase of received data as a function of the result of said comparing, by an amount enabling effecting sampling of received data by said master clock,
• sampling means for sampling said coarse phase-shifted received data to thereby form master clock-sampled received data in absolute phase synchronization with said master clock,
• means for selecting one of said master clock or said recovered clock as an output for application as an input to said data conversion means and for concomitantly selecting the associated said master clock-sampled received data or said recovered clock-sampled received data as an output for application as an input to said data conversion means,
• and go-ahead detection and generating means for detecting absence of both a multi-bit go-ahead token and intelligence-bearing data, and for generating and inserting a go-ahead token into the data stream upon detection of absence of said go-ahead token and intelligence-bearing data.

The method of absolutely synchronizing the phase of binary data with a binary master clock in which the binary data has effectively the frequency of the master clock but may be out of phase with the master clock, comprising

• forming a binary data-synchronized clock synchronized with said particular binary data,
• comparing the phase of said data-synchronized clock with the phase of said master clock,
• forming coarse phase-shifted binary data which is coarse phase-shifted relative to said particular binary data if and as may be required as a function as the coarse phase angle difference detected by said comparing and by a coarse amount enabling effective sampling thereof by said master clock,
• and sampling said course phase-shifted data to thereby provide said binary data in absolute phase synchronization with said master binary clock.

The method of absolute phase synchronizing receive data from one location with a master clock at a second location in which receive clock is the receive clock at said second location and is in substantial frequency synchronism with said master clock but of no definite phase relationship relative to master clock, comprising

• generating a master clock associated with said second location and which master clock is the time-base source of clock for said receive data,
• comparing the phase of said receive clock with the phase of said master clock,
• absolute phase-synchronizing said receive data to absolute phase synchronism with said master clock,
• said absolute phase-synchronizing being effected by coarse phase-shifting of said receive clock synchronized receive data relative to said master clock by an amount which, based on the phase difference between said receive clock and said master clock as indicated by said comparing of phases, is sufficient to enable effective sampling of said data by said master clock,
• and effectively sampling the resultant said phase-shifted data with said master clock to thereby synchronize said receive data in absolute phase with said master clock.

The method of synchronizing receive data with master clock, comprising

• generating a master clock of substantially constant frequency,
• generating a selectively variable frequency slave clock having a nominal frequency substantially corresponding to said master clock,
• comparing the phase relationship of said variable frequency slave clock with data transitions of receive data,
• selectively successively varying the frequency and phase of said variable frequency slave clock as a function of the phase relationship of said variable frequency slave clock with said data transitions of said receive data, to form recovered receive clock in substantial frequency synchronism with said receive data,
• reclocking said receive data with said variable frequency slave clock by sampling said receive data with said recovered receive clock formed by the updated said variable frequency clock to form recovered clock-synchronized receive data,
• comparing the phase of said recovered receive clock with the phase of said master clock,
• selectively shifting the phase of said recovered receive clock-synchronized receive data as a function of the amount of phase difference between said master clock and said recovered receive clock by an amount sufficient to enable effective sampling of said recovered receive clock-synchronized receive data by said master clock,
• and effectively sampling the resultant phase-shifted said recovered receive clock-synchronized receive data, to thereby form receive data in absolute phase synchronism with said master clock.