US 4,677,499 AGranted

Digital time base corrector

AssigneeSony Corporation

InventorsNorihisa Shirota, Takao Yamazaki, Seiichiro Iwase

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Abstract

There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit. A signal selecting circuit is divided into N first unit selecting circuits and a second unit selecting circuit. M of the output signals of a shift register are inputted to the first unit selecting circuits, by which one of them is selected. The outputs of the N first unit selecting circuits are supplied to the second unit selecting circuit, by which one of them is selected. A pipeline process is performed by inserting a delay circuit to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit. Further, the selecting signal can be made variable for every one clock and a delay circuit is inserted on the output side of a selecting signal forming circuit. With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.

Claims5

Dependent claims

A digital time base corrector for correcting the time base of a serial input digital information signal with a predetermined clock frequency comprising:

(A) a delay circuit supplied with said serial input digital information signal and for generating a plurality of delayed outputs therefrom, each having different respective time delays;
(B) a first group of selecting circuits, each of which is supplied with M of said delayed outputs as inputs thereof and for selecting one of said inputs, wherein M is a positive integer;
(C) a plurality of unit delay circuits, each of said delay circuits being connected to the output of a respective one of said selecting circuits and for delaying the output signal of said selecting circuit for one clock period;
(D) a second selecting circuit supplied with the outputs of said unit delay circuits and for selecting one of said outputs;
(E) a selecting signal generating circuit supplied with a digital selecting signal that determines an extent of time base correction to be applied to said input digital signal and which is varied at every clock period for generating first and second selecting signals;
and
(F) first and second register means connected respectively to said first and second selecting signals of said selecting signal generator and for delaying said first and second selecting signals, respectively, the output of said first register means being supplied to said first group of selecting circuits and the output of said second register means being supplied to said second selecting circuit.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/721,658Filed 10 Apr 1985
Priority: JP 59-7420513 Apr 1984
Granted: 30 Jun 1987
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03K 5/131
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: digitally controlled
G11B 20/18
Digital recording or reproducing: error detection or correction; Testing , e.g. of drop-outs
H04N 5/95
Regeneration of the television signal or of selected parts thereof: time-base error compensation
H03K 2005/00241
Using circuits having two logic levels: using shift registers