Semiconductor memory device with trench surrounding each memory cell

A semiconductor memory device comprising memory cells respectively located at intersections of bit and word lines arranged in a matrix form, each of said memory cells being constituted by a single insulated gate transistor and a single capacitor,

• said semiconductor memory device further comprising trenches formed in a semiconductor substrate in a direction of thickness thereof, said trenches being arranged in a matrix form when viewed from a top thereof so as to surround corresponding memory cells,
• said capacitor comprising a first insulating film formed along a lower portion of a side wall surface of each trench formed in the direction of thickness of the semiconductor substrate and a capacitor electrode formed along said first insulating film so as to fill at least a lower portion of said trench,
• said transistor comprising a gate insulating film adjacent to said capacitor and formed along an upper portion of said side wall surface of said trench, a gate electrode formed along said gate insulating film so as to fill at least an area of a remaining upper portion of said trench, said gate electrode being insulated from said capacitor electrode through a second insulating film, and a diffusion region formed in a major surface of said semiconductor substrate which is adjacent to said gate insulating film, and
• said semiconductor memory device further comprising element isolation means between two adjacent ones of said memory cells.