Simplified delay testing for LSI circuit faults
AssigneeUniversity of Southern California
InventorsMelvin A. Breuer, Navnit K. Nanda
Life of this patent
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Abstract
Thorough delay testing of a combinational logic circuit is accomplished by changing only one input at a time (a single transition), and checking the output at a predetermined short time later, and arrangements are disclosed for systematically applying to the inputs of a combinational logic circuit all possible single transitions of the binary input signals. One economical test circuit uses a conventional binary counter and an associated ring counter to generate the test signals, in addition to input switching circuits or multiplexers for steering data to the logic to be tested and control circuitry to control the test process.
Claims24
A test system for testing combinational electronic logic circuits in which the electronic logic circuit to be tested can have a plurality of inputs and outputs,
- means for coupling said combinational logic circuit to a test input circuit having at least as many inputs as the combinational logic circuit,
- a test circuit pattern generation means for applying patterns to said combinational logic circuit through said coupling means, said test circuit including means for generating all possible 1-transitions between binary input combinations which differ from one-another by only one bit transition, and which include not significantly more than 2n2.sup.n +1 transitions, where n is the number of binary inputs to the combinational circuit;
- and
- means for checking the correctness of the output of the combinational circuit during a predetermined time window following each transition.
A method for the testing for faults including delay faults in electronic combinational logic circuits having a plurality of inputs and a plurality of outputs, comprising the steps of:
- applying a series of all possible 1-transitions to the inputs of a combinational logic circuit, with the transitions being applied at predetermined times;
- and
- checking validity of the outputs from said combinational logic circuit at short time intervals after said predetermined times.
A test system for testing combinational electronic logic circuits in which the electronic logic circuit to be tested has a plurality of inputs and a plurality of outputs;
- a normal data processing input coupled said inputs to said logic circuit;
- means for switching from the normal data processing input to said combinational logic circuit to a test input circuit having at least as many inputs as the combinational logic circuit;
- a test circuit pattern generation means for coupling to said switching means, said test circuit including means for generating all possible transitions between binary input combinations which differ from one-another by only one bit, and which include not significantly more than 2n2.sup.n transitions, where n is the number of binary inputs to the combinational circuit;
- and
- means for checking the correctness of the outputs of the combinational circuit during a predetermined time window following each transition.
A test system for testing combinational electronic logic circuits in which the electronic logic circuit to be tested has a plurality of inputs and a plurality of outputs:
- means for coupling said combinational logic circuit to a test input circuit having at least as many inputs as the combinational logic circuit,
- a test circuit pattern generation means for applying test patterns to said logic circuit through said coupling means, said test circuit including means for generating all possible transitions between binary input combinations which differ from one-another by only one bit transition, and which include not significantly more than 2n2.sup.n +1transitions, where n is the number of binary inputs to the combinational circuit;
- said test system including a set of registers coupled to the inputs of said combinational logic circuit, a binary counter, a ring counter having an output, and means for changing the state of individual stages of said set of registers in accordance with the output from said ring counter and said binary counter;
- means for checking the correctness of the output of the combinational circuit during a predetermined time window following each transition.
A test system for testing combinational electronic logic circuits in which the electronic logic circuit to be tested has a plurality of inputs and outputs,
- means for coupling said combinational logic circuit to a test input circuit having at least as many inputs as the combinational logic circuit,
- a test circuit pattern generation means for applying test patterns to said logic circuit through said coupling means, said test circuit means including means for generating only transitions between binary input combinations which differ from one-another by only one bit transition;
- said test system including a set of registers coupled to the input of said combinational logic circuit, a ring counter having an output, and means for changing the state of individual stages of said set of registers in accordance with the output from said ring counter;
- and
- means for checking the correctness of the outputs of the combinational circuit during a predetermined time window following each transition, said time window corresponding to a cycle of the logic circuit under test.
Dependencies are inferred from the claim text.