Loading patent…
AssigneeAdvanced Micro Devices, Inc.
InventorsMark S. Young, John Drew, Michael C. Shebanow
Estimating the term…
A method and apparatus for generating a check sum and a syndrome for detecting errors in a series of bytes comprising a plurality of stages, each stage comprising a plurality of networks of exclusive OR gates, a memory and an exclusive OR gate for exclusively ORing the outputs of the networks resulting from a byte transmitted therethrough with the results stored in a memory in a previous stage due to a previous byte. Each of the stages and the networks therein correspond to a term in a Reed-Solomon polynomial. Except for differences in the number and construction of the networks in each stage, each of the stages are substantially identical and can be selectively used for detecting single and double burst errors.
In an error detection and correction apparatus comprising a series of stages, each of said stages having a first and a second network of exclusive OR gates, a single exclusive OR gate having a first input, a second input and an output, a memory device, means for selectively coupling said first input to said first network and said first location, means for coupling said output to said memory device, means for selectively coupling said second input to the output of the memory device in another stage and to said second network and means for coupling the output of said memory device in each stage to said second network;
In an error detection and correction apparatus comprising a series of stages, each of said stages having a first and a second network of exclusive OR gates, a single exclusive OR gate having a first input, a second input and an output, a memory device, means for selectively coupling said first input to said first network and said first location, means for coupling said output to said memory device, means for selectively coupling said second input to the output of the memory device in another stage and to said second network and means for coupling the output of said memory device in each stage to said second network;
A method for generating a check sum for detecting errors in a series of bytes in an apparatus having a memory in each of a series of stages comprising the steps of:
A method of generating a syndrome for detecting errors in a series of bytes comprising a data record and a check sum comprising the steps of:
An apparatus for generating a check sum and a syndrome for detecting errors in a series of bytes comprising:
Dependencies are inferred from the claim text.