High-speed full differential amplifier with common mode rejection

A full differential amplifier circuit receiving a pair of differential inputs and providing a pair of differential outputs,

• an input differential stage for receiving said differential inputs and for conducting a constant current, said input differential stage means having a pair of coupled transistor means respectively driving a pair of feedback current mirror means providing signals,
• a pair of mirror stage means for level shifting, converting and communicating said signals cross connected from said feedback current mirror means,
• a pair of cascode stage means each for receiving a respective inversely changing portion of said signals from said mirror stage means and each providing one of said pair of differential outputs inversely changing, each of said cascode stage means receiving a first and a second portion of said inversely changing portions of said signals, said first and second portions of said signals synchronously changing respecting the other portion of said signals, each of said first and second portions of said signals respectively driving and dynamically biasing a respective inversely conducting first and second portion of said cascode stage means,
• resistive network means for providing an average common mode signal from said pair of differential outputs, and
• a pair of feedback differential stage means for receiving said average common mode signal and a bias reference and for conducting said constant current, each of said feedback differential stage means having a pair of coupled transistor means respectively driving a pair of feedback current mirror means each respectively providing common mode rejection signals to respective ones of said pair of said cascode stage means serving to reject common mode signals from respective ones of said pair of differential outputs.

A method of producing differential output signals responsive to differential input signals comprising the steps of,

• determining the difference between the differential input signals,
• conducting respective portions of a constant current through a pair of feedback current mirror loads,
• shifting, converting and communicating signals from said feedback current mirror loads,
• inversely driving a pair dynamically biased cascode stages with said shifted, converted and communicated signals from said feedback current mirror loads, each of said cascode stages providing one of said differential output signals,
• averaging said differential output signals and providing an average common mode signal,
• determining the difference between a bias reference and said average common mode signal,
• providing common mode rejection current signals from at least one pair of other feedback current mirror loads, said signals responsive to said difference between said bias reference and said common mode signal, and
• synchronously driving said dynamically biased cascode stage towards said bias reference with said common mode rejection current signals whereby said common mode signals are eliminated from said differential outputs signals through negative feedback.