Back to results
US 4,665,374 AGranted
Monolithic programmable signal processor using PI-FET taps
AssigneeAllied Corporation
InventorMohammed A. Fathimulla
Life of this patent
Estimating the term…
Abstract
A monolithic programmable signal processor with piezoelectric insulator FETs and an InP substrate. The piezoelectric insulator FETs are capable of being constructed on the same substrate with circuits associated with the signal processor and optical components.
Claims17
A monolithic programmable signal processor comprising:
- a substrate, having a first conductivity type, selected from the group of semiconductors comprising silicon (Si) and indium phosphide (InP);
- a first piezoelectric layer formed on a first portion of said substrate;
- at least one transducer for generating surface acoustic waves propagating along the surface of said first piezoelectric layer along a predetermined path;
- a set of parallel source electrodes having a second conductivity type formed in said substrate along said predetermined path in the region underlying said first piezoelectric layer, said parallel source electrodes being disposed perpendicular to said predetermined path of said surface acoustic waves and said second cuductivity type being opposite said first conductivity type;
- a set of parallel drain electrodes having said second conductivity type interdigitally formed in said substrate between said first set of parallel source electrodes, each of said interdigitally formed parallel source and drain electrodes being separated from each other by a predetermined interelectrode space;
- and
- gate means formed on the surface of said piezoelectric layer for controlling the conductivity between said gate and source electrodes, said gate means covering at least the portion of said piezoelectric layer which overlays each of said interelectrode spaces.
4 more elements
A monolithic programmable signal processor comprising:
- an InP substrate having a p-type conductivity;
- an insulating layer disposed on the surface of said substrate;
- a ZnO piezoelectric layer selectively formed on a first portion of said insulating layer;
- at least one transducer disposed on said substrate for generating surface acoustic waves which propagate along the surface of said piezoelectric layer along a predetermined path;
- a set of parallel source electrodes having an n-type conductivity formed in said InP substrate along said predetermined path in the region underlying said ZnO piezoelectric layer, said parallel source electrodes being disposed perpendicular to said predetermined path of said surface acoustic waves;
- a set of parallel drain electrodes, having an n-type conductivity, interdigitally formed in said InP substrate between said set of parallel source electrodes, said interdigitally formed parallel source and drain electrodes being separated from each other by a predetermined interelectrode space;
- and
- gate means formed on the surface of said ZnO piezoelectric layer for controlling the conductivity between said gate and source electrodes, said gate means covering at least the portion of said piezoelectric layer which overlays each of said interelectrode spaces.
5 more elements
A monolithic programmable signal processor comprising:
- an InP substrate having a p-type conductivity;
- an insulating layer disposed on the surface of said substrate;
- a ZnO piezoelectric layer selectively formed on a first portion of said insulating layer;
- at least one transducer disposed on said substrate for generating surface acoustic waves which progagate along the surface of said piezoelectric layer along a predetermined path;
- a set of parallel source electrodes having an n-type conductivity formed in said InP substrate along said predetermined path in the region underlying said ZnO piezoelectric layer, said parallel source electrodes being disposed perpendicular to said predetermined path of said surface acoustic waves;
- a set of parallel drain electrodes, having an n-type conductivity, interdigitally formed in said InP substrate between said set of parallel source electrodes, said interdigitally formed parallel source and drain electrodes being separated from each other by a predetermined interelectrode space;
- and
- gate means formed on the surface of said ZnO piezoelectric layer for controlling the conductivity between the gate and source electrodes, said gate means covering the portion of said ZnO piezoelectric layer which overlays said gate electrodes, said source electrodes, and said interelectrode spaces.
5 more elements
Dependencies are inferred from the claim text.