Random/serial access mode selection circuit for a video memory system

A computer system comprising:

• (a) video display means having video signal input means for receiving bit-serial video data for display of data on a screen, said video singal input means connected to a video data path,
• (b) bit-mapped video memory means including at least one video memory device, each said video memory device constructed in a single semiconductor integrated circuit and having both bit-serial and single-bit access ports, each said memory device comprising:
• (i) an array of rows and columns of read/write memory cells,
• (ii) addressing means for selecting rows, or selecting rows and columns, in response to address bits applied to address terminals of the device and in response to an address strobe applied to a control terminal of said device,
• (iii) serial register means, and means for loading data from a row of said cells selected by said addressing means to said serial register means,
• (iv) a serial data output terminal connected to said serial register means, said output terminal connected to said video data path and thereby coupled to said video signal input means,
• (v) at least one single-bit data input terminal, and at least one single-bit data output terminal, and means connecting said at least one single-bit data input and data output terminals to a column or columns selected by said addressing means,
• (vi) and control means receiving said address strobe and receiving a control signal from another terminal of said device, and selecting serial access responsive to receiving said control signal prior to said address strobe, and selecting single-bit access responsive to receiving said control signal a predetermined time after receiving said address strobe,
• (c) and microprocessor means having bit-parallel bus means separate from said video data path, said bus means coupled to said bit-mapped video memory means, said microprocessor means applying addresses to said address terminals of said at least one video memory device via said bus means for selecting said rows for loading to said serial register means and for selecting rows and columns for said single-bit access, said microprocessor means applying data to said at least one data input terminal of the device via said bus means for writing into said memory cells, said data being supplied to said at least one single-bit data terminal during the time that at least some of the bit-serial video data is being applied to said video signal input means via said video data path, and said microprocessor means applying said address strobe and said control signal to said memory means.