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US 4,663,730 AGranted
Sequence controller
AssigneeFanuc Corporation
InventorYoshiaki Ikeda
Life of this patent
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Abstract
Disclosed herein is a sequence controller wherein predetermined sequence processing can be executed by a built-in processor (2) in accordance with data transferred periodically from a processor (1) in a numerical control device (NC). The NC processor generates an interrupt signal (e) each time a transfer of data is completed. On the basis of the interrupt signal, the built-in processor in the sequence controller starts the predetermined sequence processing.
Claims4
A sequence controller executing sequence processing, comprising:
- built-in processor means for performing the sequence processing in dependence upon sequence processing data and generating a cycle end signal upon completion of a cycle of the sequence processing;
- and
- main processor means, connected to said built-in processor means, for generating and transferring the sequence processing data to said built-in processor means regardless of whether the sequence processing is being performed, generating a transfer end signal, independently of the cycle end signal, indicating completion of the transfer of the sequence processing data and generating an interrupt signal in response to the transfer end signal and the cycle end signal, said built-in processor means starting predetermined sequence processing upon receiving the interrupt signal.
A sequence controller executing sequence processing, comprising:
- built-in processor means for performing the sequence processing in dependence upon sequence processing data, comprising:
- a sequence controller processor for controlling the sequence processing and generating a cycle end signal indicating completion of a cycle of predetermined sequence processing;
- and
- a sequence controller buffer connected to said sequence control processor;
- and
- main processor means for generating and transferring the sequence processing data to said built-in processor means regardless of whether the processing is being performed, comprising:
- a numerical control processor for performing numerical control and generating a transfer end signal independently of the cycle end signal, the transfer end signal indicating completion of the transfer of the sequence processing data;
- a numerical control buffer connected to said numerical control processor and said sequence controller buffer;
- and
- an interrupt generating circuit, connected to said sequence controller processor and said numerical control processor, for generating an interrupt signal in response to the transfer end signal and the cycle end signal, said built-in processor means starting the predetermined sequence processing upon receiving the interrupt signal.
7 more elements
Dependencies are inferred from the claim text.