Method for fabricating a CMOS well structure
AssigneeTexas Instruments Incorporated
InventorSatwinder Malhi
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Abstract
A process is disclosed for fabricating N-wells in a P-type substrate. An N-type epitaxial layer is formed on the surface of a P+ substrate. The N-type epitaxial layer is then masked and a doubly charged boron implant is performed on the exposed areas of the N-type epitaxial layer. Because of the lower mass of boron, a common production 200 kiloelectron volt implanter provides sufficient implantation energy to doubly charged boron to provide a P region which extends through the N-type epitaxial layer. The remaining N-type portions of the epitaxial layer provide N-wells for the fabrication of complementary field effect transistor circuitry.
Claims2
A process for fabricating an N-well structure. comprising the steps of:
- forming a semiconductor epitaxial layer which is doped n-type on a p-type semiconductor substrate;
- implanting doubly-charged boron (B++) ions into said epitaxial layer except in selected regions of said epitaxial layer, said implantation having a sufficient energy and concentration to completely counterdope said epitaxial layer to p-type except in said selected regions.
A process for fabricating an N well structure, comprising the steps of:
- forming an N type semiconductor epitaxial layer having a thickness of approximately 3 microns on a P type semiconductor substrate;
- implanting doubly charged boron ions (B++ ions) said epitaxial layer except in selected regions of said epitaxial layer, said implantation having an energy of approximately 400 kiloelectronvolts and a concentration of approximately 1E13/cm-squared;
- and
- annealing and driving in boron ions implanted by said implanting step, to completely counterdope said epitaxial layer to said second conductivity type.
Dependencies are inferred from the claim text.