High speed testing of integrated circuit
AssigneeTexas Instruments Incorporated
InventorBao G. Tran
Life of this patent
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Abstract
A register of the type used on as address counter in a dynamic RAM is tested by a method which does not require cycling through every possible value of the register contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the contents checked by an AND or OR gate, producing a one-bit output which is monitored off-chip. Then, the carry feedback path to the counter register is altered, as by inverting all but the LSB, and the contents again checked, using the one-bit output via the AND or OR. In this manner, the operation of the counter is tested in three cycles.
Claims5
A semiconductor memory device comprising:
- an array of rows and columns of storage cells, each storage cell having a storage capacitor which decays with time,
- addressing means for activating one of said rows of storage cells,
- an address input to said device, said address input including terminals of the device,
- an address counter having a plurality of bits and an internal carry circuit,
- multiplex means to apply an address either from said address input of the device or from said address counter to said addressing means,
- and testing means for testing the operation of said counter without counting through all combinations of said bits, including:
- logic circuit means to detect the bits in said counter and to produce a 1-bit output at a terminal of said device indicating either all 1's or all 0's in said counter,
- and means coupled to said internal carry circuit for altering said carry circuit in response to a control input.
Dependencies are inferred from the claim text.