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AssigneeHitachi, Ltd.
InventorsMasakazu Aoki, Yoshinobu Nakagome, Masashi Horiguchi, Shinichi Ikenaga, Katsuhiro Shimohigashi
Estimating the term…
In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.
A semiconductor memory having multiple level storage structure at least comprising a memory array including a plurality of memory cells respectively having at least one storage capacitor, an address selecting means which designates location of each memory cell, data lines which transfer data through connections to said memory cells and data writing and reading means being connected to said data lines, said memory further comprising
Dependencies are inferred from the claim text.