Elementary logic circuit obtained by means of field effect transistors of gallium arsenide and compatible with the ECL 100 K technology

An elementary logic circuit having Schottky barrier field effect transistors of gallium arsenide and comprising a differential amplifier, a load register R.sub.1 and a transistor T.sub.1, a first branch of said amplifier being formed by the transistor T.sub.1, which is of the enhancement type, controlled by an input signal E and connected by its drain, at which a signal S.sub.1 is available, to a first supply voltage terminal (V.sub.DD) through the load resistor R.sub.1, a load resistor R.sub.2 and an enhancement type transistor T.sub.2, a second branch of said amplifier being formed by the enhancement transistor T.sub.2 controlled by a reference signal and connected by its drain, at which a signal S.sub.2 is available, to the first supply source terminal (V.sub.DD) through the load resistor R.sub.2, a transistor T.sub.5, the coupled sources of the transistors T.sub.1 and T.sub.2 being supplied with current through the transistor T.sub.5 of the charge depletion type connected in a common gate-source arrangement to a second supply potential terminal (V.sub. SS), said circuit further comprising two paired level translator stages, the first of which comprises a diode D.sub.4 and a transistor T.sub.4 connected in a common drain arrangement to the first supply voltage terminal (V.sub.DD), controlled by the signal S.sub.1 of the first branch of the differential amplifier and connected by its source to the anode of the diode D.sub.4, and the second of which comprises a diode D.sub.3, and transistor T.sub.3 connected in a common drain arrangement to the first voltage supply terminal (V.sub.DD), controlled by the signal S.sub.2 of the second branch of the differential amplifier and connected by its source to the anode of the diode D.sub.3, the transistors T.sub.3 and T.sub.4 of the level translator stages being of the enhancement type, further comprising resistors R.sub.3 and R.sub.4, the cathodes of the diodes D.sub.3 and D.sub.4 of the level translator stages being connected to the second supply voltage terminal (V.sub.SS) through the resistors R.sub.3 and R.sub.4, which are paired, the output signal S, which is the inverse value of the input signal E of the elementary logic circuit, being provided at the cathode of the diode D.sub.4 of the first level translator stage, the output signal S, complementary to the output signal S, being provided at the cathode of the diode D.sub.3 of the second level translator stage, and the output signal S of the elementary logic circuit comprising a reference signal which controls the transistor T.sub.2 of the second branch of the differential amplifier.