IGFET comparator circuit having greater control of intended offset voltage

The combination comprising:

• first, second, third, fourth and fifth, insulated-gate field-effect transistors (IGFETs), each IGFET having source and drain electrodes defining the ends of a conduction path and a control electrode;
• a bias terminal for the application thereto of a fixed bias potential;
• first and second power terminals for the application therebetween of an operating potential;
• first and second signal input terminals for the application therebetween of variable differential input signals;
• means connecting the source-to-drain path of said first IGFET between said first power terminal and a first node;
• means connecting the source drain path of said second IGFET between said first node and a second node;
• means connecting the source-to-drain path of said third IGFET between said first node and a third node;
• means connecting the control electrode of said second IGFET to said first signal input terminal and means connecting the control electrode of said third IGFET to said second signal input terminal;
• means connecting the source-to-drain paths of said fourth and fifth IGFET in series between said first power terminal and said second node;
• means connecting the control electrodes of said first and fourth IGFETs to said bias terminal;
• means connecting the control electrode of said fifth IGFET to said first signal input terminal and its drain electrode to said second node;
• and
• current mirror means connected between said second and third nodes and said second power terminal tending to pass a like current between said third node and said second power terminal as flows between said second node and said second power terminal.

A comparator circuit comprising:

• a differential input stage comprising first and second insulated-gate field-effect transistors (IGFETs), each IGFET having source and drain electrodes defining the ends of a conduction path and a control electrode and said first and second IGFETs having their source electrodes connected in common to a first current source, their control electrodes connected to first and second signal input terminals, respectively, and their drains connected to first and second nodes, respectively, said first current source including a third IGFET having its source-to-drain path connected between a first point of operating potential and the source electrodes of said first and second IGFETs, and its gate electrode connected to a bias terminal;
• means for applying variable differential signals to said first and second signal input terminals and to the control electrodes of said first and second IGFETs;
• a current mirror connected between said first and second node for passing all the current flowing in said first node and tending to pass the same current in said second node;
• and
• an offset current generator connected to said first node comprising:
• (a) a second current source for passing a current proportional to the current produced by said first current source;
• and (b) input signal responsive means serially connected between said second current source and said first node for maintaining the current flowing from said second current source into said first node proportional to the current in said first IGFET, said second current source including a fourth IGFET and said input signal responsive means includes a fifth IGFET, wherein the conduction paths of said fourth and fifth IGFETs are connected in series between said first point of operating potential and said first node;
• and wherein the gate electrode of said fourth IGFET is connected to said bias terminal, and wherein the gate electrode of said fifth IGFET is connected to said first signal input terminal.