Voltage detection circuit for detecting input voltage larger in absolute value than power supply voltage

A programmable read only memory device comprising:

• a programming terminal supplied with a programming voltage;
• a power terminal supplied with a power voltage;
• a reference terminal supplied with a reference potential;
• a plurality of memory cells;
• means responsive to address signals for selecting at least one of said memory cells;
• a detection circuit for detecting an application of said programming voltage higher in absolute value than said power voltage and producing a detection signal;
• and
• means responsive to said detection signal for supplying said programming voltage to the selected memory cell;
• said detection circuit including
• a first node and a second node;
• a first field effect transistor connected between said programming terminal and said first node and having a gate of said first field effect transistor connected to a drain of said first field effect transistor;
• a second field effect transistor of a first channel type connected between said first node and said second node and having a gate of said second field effect transistor connected directly to said power supply;
• a third field effect transistor of a second channel type connected between said second node and said reference terminal and having a gate of said third field effect transistor connected directly to said power supply;
• and
• an inverter operative with said power voltage and said reference potential and having its input terminal connected to said second node, said inverter producing said detection signal.

An integrated circuit comprising:

• a power terminal supplied with a power voltage;
• a reference terminal supplied with a reference potential;
• a signal terminal;
• a transistor circuit supplied through said signal terminal with an input signal, said input signal taking a level that is within a range between said power voltage and said reference potential upon a steady operation mode, said signal terminal being supplied with a testing voltage upon a test operation mode, said testing voltage taking a level that is higher in absolute value than said power voltage;
• a detection circuit detecting an application of said testing voltage to said signal terminal;
• and
• a test circuit testing said transistor circuit in response to said detection signal;
• said detection circuit including
• a first field effect transistor connected between said signal terminal and a first node and having a gate of said first field effect transistor connected to a drain of said first field effect transistor;
• a second field effect transistor of a first conductivity type connected between said first node and a second node and having a gate of said second field effect transistor connected directly to said power terminal;
• and
• a third field effect transistor of a second conductivity type connected between said second node and said reference terminal and having a gate of said third field effect transistor connected directly to said power terminal.